JAJSNC5 april   2023 LM5171-Q1

ADVANCE INFORMATION  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 7.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 7.3.3  High Voltage Inputs (HV1, HV2)
      4. 7.3.4  Current Sense Amplifier
      5. 7.3.5  Control Commands
        1. 7.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 7.3.5.2 Direction Command (DIR1 and DIR2)
        3. 7.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 7.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 7.3.6.1 Individual Channel Current Monitor
        2. 7.3.6.2 Multiphase Total Current Monitoring
      7. 7.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 7.3.8  Inner Current Loop Error Amplifier
      9. 7.3.9  Outer Voltage Loop Error Amplifier
      10. 7.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 7.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 7.3.10.2 DEM Programming
        3. 7.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 7.3.10.4 SS Pin as the Restart Timer
      11. 7.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 7.3.12 Emergent Latched Shutdown (DT/SD)
      13. 7.3.13 PWM Comparator
      14. 7.3.14 Oscillator (OSC)
      15. 7.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 7.3.16 Overvoltage Protection (OVP)
      17. 7.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 7.3.17.1 Multiphase in Star Configuration
        2. 7.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 7.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Programming
      1. 7.4.1 Dynamic Dead Time Adjustment
      2. 7.4.2 UVLO Programming
    5. 7.5 I2C Serial Interface
      1. 7.5.1 REGFIELD Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 Typical Application
      1. 8.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Determining the Duty Cycle
          2. 8.2.1.2.2  Oscillator Programming
          3. 8.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.2.1.2.4  Current Sense (RCS)
          5. 8.2.1.2.5  Current Setting Limits (ISETx)
          6. 8.2.1.2.6  Peak Current Limit
          7. 8.2.1.2.7  Power MOSFETS
          8. 8.2.1.2.8  Bias Supply
          9. 8.2.1.2.9  Boot Strap
          10. 8.2.1.2.10 OVP
          11. 8.2.1.2.11 Dead Time
          12. 8.2.1.2.12 Channel Current Monitor (IMONx)
          13. 8.2.1.2.13 UVLO Pin Usage
          14. 8.2.1.2.14 HVx Pin Configuration
          15. 8.2.1.2.15 Loop Compensation
          16. 8.2.1.2.16 Soft Start
          17. 8.2.1.2.17 PWM to ISET Pins
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 I2C Serial Interface

In LM5171, I2C communication is available when the UVLO pin is > 1.5V and the configuration is complete. VDD pin voltage falling below 4.5V VDDUV disables the communication, but as long as it stays above 2.5V (the lower threshold), it does not require reconfiguring to enter the I2C communication when VDD goes out of VDDUV.

I2C Bus Operation

The I 2 C bus is a communications link between a Controller and a series of Peripheral devices. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the Controller in all cases where the serial data line is bi-directional for data communication between the Controller and the Peripheral terminals. Each device has an open-drain output to transmit data on the serial data line (SDA). An external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. The device hosts a Peripheral I 2 C interface that supports standard-mode, fast-mode and fast-mode plus operation with data rates up to 100 kbit/s, 400 kbit/s and 1000 kbit/s respectively and auto-increment addressing compatible to I 2 C standard 3.0. Data transmission is initiated with a start bit from the controller as shown in the figure below. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device receives serial data on the SDA input and check for valid address and control information. If the peripheral address bits are set for the device, then the device issues an acknowledge pulse and prepares to receive the register address and data. Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. The I 2 C interfaces auto-sequence through register addresses, so that multiple data words can be sent for a given I 2 C transmission.
GUID-DBD7D4CD-EB70-4E75-BFA5-3403A709423D-low.gif Figure 7-33 I 2 C START / STOP / ACKNOWLEDGE Protocol
GUID-0D70A46A-43D3-4CC0-969F-73DC98D2E8C5-low.gif Figure 7-34 I 2 C Data Transmission Timing
GUID-15BD41CB-B638-40E7-8359-A6E48FD3A891-low.gif Figure 7-35 I 2 C Data Transmission Timing for maximum rise/fall times.

Clock Stretching

Clock stretching is not supported. If the device is addressed while busy and not able to process the received data, it does not acknowledge the transaction.

Data Transfer Formats

The device supports four different read/write operations:

  • Single read from a defined register address.
  • Single write to a defined register address.
  • Sequential read starting from a defined register address
  • Sequential write starting from a defined register address

Single READ From a Defined Register Address

Figure 7-36 shows the format of a single read from a defined register address. First, the Controller issues a start condition followed by a seven-bit I 2 C address. Next, the Controller writes a zero to signify that it conducts a write operation. Upon receiving an acknowledge from the Peripheral the Controller sends the eight-bit register address across the bus. Following a second acknowledge the device sets the internal I 2 C register number to the defined value. Then the Controller issues a repeat start condition and the seven-bit I 2 C address followed by a one to signify that it conducts a read operation. Upon receiving a third acknowledge, the Controller releases the bus to the device. The device then returns the eight-bit data value from the register on the bus. The Controller does not acknowledge (nACK) and issues a stop condition. This action concludes the register read.


GUID-44EFF3F2-012C-48CB-B939-7994F5E38B7E-low.gif
Figure 7-36 Single READ From a Defined Register Address

Sequential READ Starting From a Defined Register Address

A sequential read operation is an extension of the single read protocol and shown in Figure 7-37. The Controller acknowledges the reception of a data byte, the device auto increments the register address and returns the data from the next register. The data transfer is stopped by the Controller not acknowledging the last data byte and sending a stop condition.


GUID-84E7DC4F-75C8-4CD5-833A-DDE23A4D0A9E-low.gif
Figure 7-37 Sequential READ Starting From A Defined Register Address

Single WRITE to a Defined Register Address

Figure 7-38 shows the format of a single write to a defined register address. First, the Controller issues a start condition followed by a seven-bit I 2 C address. Next, the Controller writes a zero to signify that it wishes to conduct a write operation. Upon receiving an acknowledge from the Peripheral, the Controller sends the eight-bit register address across the bus. Following a second acknowledge the device sets the I 2 C register address to the defined value and the Controller writes the eight-bit data value. Upon receiving a third acknowledge the device auto increments the I 2 C register address by one and the Controller issues a stop condition. This action concludes the register write.


GUID-6A20FEEC-16A3-4B35-BBE0-E2059FDCD5B6-low.gif
Figure 7-38 Single WRITE to Defined Register Address

Sequential WRITE Starting From A Defined Register Address

A sequential write operation is an extension of the single write protocol and shown in Figure 7-39. If the Controller does not send a stop condition after the device has issued an ACK, the device auto increments the register address by one and the Controller can write to the next register.


GUID-82FE435C-99F0-45F6-8449-3ED8ABD8E01E-low.gif
Figure 7-39 Sequential WRITE Starting At A Defined Register Address