JAJSNC5 april 2023 LM5171-Q1
ADVANCE INFORMATION
The LM5171-Q1 integrates a LDO driver to drive an external N-channel MOSFET to generate 9V bias supply at the VCC pin. The VCC pin can also accept an external supply of 9.5 V to 12 V and the device turns off the LDO driver to save the power dissipation in the external LDO MOSFET. Figure 7-1 shows typical connections of the bias supply.
When external supply is used, it is recommended to add a block diode to prevent from discharging the VCC during transient in the external supply. If an external supply voltage is greater than 12 V, a 10-V LDO or switching regulator must be used to produce 10 V for VCC. The VCC voltage is directly fed to the low-side MOSFET drivers. A 1-μF to 2.2-μF ceramic capacitor must be placed between the VCC and PGND pins to bypass the driver switching currents. For the LDO MOSFET, it is recommended to have the Ciss around 300pF (TBD) or below.
The internal VCC undervoltage (UV) detection circuit monitors the VCC voltage. When the VCC voltage falls below 8 V on the falling edge, the LM5171-Q1 is held in the shutdown state. For normal operation, the VCC and voltage must be greater than 8.5 V on the rising edge.
Once the VCC voltage is above the VCC_UV, the VDD and VREF regulator turns on to establish 5.0 V and 3.5 V, respectively. The VDD regulator can supply up to 10mA to the external circuit. The VREF is 1% accurate reference voltage for the external circuit us use, and it has a loading capability of 2mA. A 0.1 to 1.0 μF ceramic capacitor must be placed between VDD and AGND pins, and 0.01 μF between VREF and AGND pins, respectively.