7.6 Low Dropout Regulators, LDO1 And LDO2
Unless otherwise noted, VIN = 3.6 V, CIN = 1 µF, COUT = 0.47 µF, and TJ = 25°C.(1)(2)(3)(4)(5)(6)(7)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VIN
|
Operational voltage range |
VINLDO1 and VINLDO2 PMOS pins(8)
|
1.74(9)
|
|
5.5(9)
|
V |
VOUT Accuracy |
Output voltage accuracy (default VOUT) |
Load current = 1 mA |
–3%(9)
|
|
3%(9)
|
|
ΔVOUT
|
Line regulation |
VIN = (VOUT + 0.3 V) to 5 V,
(7), load current = 1 mA |
|
|
0.15(9)
|
%/V |
Load regulation |
VIN = 3.6 V,
Load current = 1 mA to IMAX
|
|
|
0.011(9)
|
%/mA |
ISC
|
Short circuit current limit |
LDO1-2, VOUT = 0 V |
|
500 |
|
mA |
VIN – VOUT
|
Dropout voltage |
Load current = 50 mA
(5)
|
|
30 |
200(9)
|
mV |
PSRR |
Power supply ripple rejection |
ƒ = 10 kHz, load current = IMAX
|
|
45 |
|
dB |
eN
|
Supply output noise |
10 Hz < F < 100 KHz |
|
80 |
|
µVrms |
IQ(6)(10)
|
Quiescent current on |
IOUT = 0 mA |
|
40 |
|
µA |
Quiescent current on |
IOUT = IMAX
|
|
60 |
|
µA |
Quiescent current off |
EN is de-asserted(11)
|
|
0.03 |
|
µA |
TON
|
Turnon time |
Start-up from shutdown |
|
300 |
|
µs |
COUT
|
Output capacitor |
Capacitance for stability
0°C ≤ TJ ≤ 125°C |
0.33(9)
|
0.47 |
|
µF |
−40°C ≤ TJ ≤ 125°C |
0.68 |
1 |
|
µF |
ESR |
5(9)
|
|
500(9)
|
mΩ |
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum (MIN) and maximum (MAX) limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm.
(3) CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(4) The device maintains a stable, regulated output voltage without a load.
(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value.
(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.
(7) VIN minimum for line regulation values is 1.8 V.
(8) Pins 24, 19 can operate from VIN min of 1.74 V to a VIN max of 5.5 V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output.
(9) Limits apply over the entire junction temperature range for operation, −40°C to +125°C.
(10) The IQ can be defined as the standing current of the LP3907 when the I2C bus is active and all other power blocks have been disabled with the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the LP3907 is powered using a battery.
(11) The IQ exhibits a higher current draw when the EN pin is de-asserted because the I2C buffer pins draw an additional 2 µA.