JAJSED9U
June 2007 – January 2018
LP3907
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
代表的なアプリケーション回路
4
改訂履歴
5
デバイス比較表
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions (Bucks)
7.4
Thermal Information
7.5
General Electrical Characteristics
7.6
Low Dropout Regulators, LDO1 And LDO2
7.7
Buck Converters SW1, SW2
7.8
I/O Electrical Characteristics
7.9
Power-On Reset (POR) Threshold/Function
7.10
I2C Interface Timing Requirements
7.11
Typical Characteristics — LDO
7.12
Typical Characteristics — Bucks
7.13
Typical Characteristics — Buck1
7.14
Typical Characteristics — Buck2
7.15
Typical Characteristics — Bucks
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
DC-DC Converters
8.3.1.1
Linear Low Dropout Regulators (LDOs)
8.3.1.2
No-Load Stability
8.3.1.3
LDO and LDO2 Control Registers
8.3.2
SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters
8.3.2.1
Functional Description
8.3.2.2
Circuit Operation Description
8.3.2.3
PWM Operation
8.3.2.4
Internal Synchronous Rectification
8.3.2.5
Current Limiting
8.3.2.6
PFM Operation
8.3.2.7
SW1, SW2 Operation
8.3.2.8
SW1, SW2 Control Registers
8.3.2.9
Soft Start
8.3.2.10
Low Dropout Operation
8.3.2.11
Flexible Power Sequencing of Multiple Power Supplies
8.3.2.12
Power-Up Sequencing Using the EN_T Function
8.3.3
Flexible Power-On Reset (Power Good with Delay)
8.3.4
Undervoltage Lockout
8.4
Device Functional Modes
8.4.1
Shutdown Mode
8.5
Programming
8.5.1
I2C-Compatible Serial Interface
8.5.1.1
I2C Signals
8.5.1.2
I2C Data Validity
8.5.1.3
I2C Start and Stop Conditions
8.5.1.4
Transferring Data
8.5.2
Factory Programmable Options
8.6
Register Maps
8.6.1
LP3907 Control Registers
8.6.1.1
Interrupt Status Register (ISRA) 0x02
8.6.1.2
Control 1 Register (SCR1) 0x07
8.6.1.3
EN_DLY Preset Delay Sequence After EN_T Assertion
8.6.1.4
Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10
8.6.1.5
Buck and LDO Status Register (BKLDOSR) – 0x11
8.6.1.6
Buck Voltage Change Control Register 1 (VCCR) – 0x20
8.6.1.7
Buck1 Target Voltage 1 Register (B1TV1) – 0x23
8.6.1.8
Buck1 Target Voltage 2 Register (B1TV2) – 0x24
8.6.1.9
Buck1 Ramp Control Register (B1RC) - 0x25
8.6.1.10
Buck2 Target Voltage 1 Register (B2TV1) – 0x29
8.6.1.11
Buck2 Target Voltage 2 Register (B2TV2) – 0x2A
8.6.1.12
Buck2 Ramp Control Register (B2RC) - 0x2B
8.6.1.13
Buck Function Register (BFCR) – 0x38
8.6.1.14
LDO1 Control Register (LDO1VCR) – 0x39
8.6.1.15
LDO2 Control Register (LDO2VCR) – 0x3A
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Custom Design With WEBENCH® Tools
9.2.2.2
Component Selection
9.2.2.2.1
Inductors for SW1 And SW2
9.2.2.2.1.1
Method 1:
9.2.2.2.1.2
Method 2:
9.2.2.2.2
External Capacitors
9.2.2.3
LDO Capacitor Selection
9.2.2.3.1
Input Capacitor
9.2.2.3.2
Output Capacitor
9.2.2.3.3
Capacitor Characteristics
9.2.2.3.4
Input Capacitor Selection for SW1 And SW2
9.2.2.3.5
Output Capacitor Selection for SW1, SW2
9.2.2.3.6
I2C Pullup Resistor
9.2.2.4
Operation Without I2C Interface
9.2.2.4.1
High VIN High-Load Operation
9.2.2.4.2
Junction Temperature
9.2.3
Application Curves
10
Power Supply Recommendations
10.1
Analog Power Signal Routing
11
Layout
11.1
DSBGA Layout Guidelines
11.2
Layout Example
11.3
Thermal Considerations of WQFN Package
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
開発サポート
12.1.1.1
WEBENCH®ツールによるカスタム設計
12.2
ドキュメントのサポート
12.2.1
関連資料
12.3
商標
12.4
ドキュメントの更新通知を受け取る方法
12.5
コミュニティ・リソース
12.6
静電気放電に関する注意事項
12.7
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
YZR|25
MXBG279
RTW|24
MPQF167C
サーマルパッド・メカニカル・データ
RTW|24
QFND450A
発注情報
jajsed9u_oa
jajsed9u_pm
Device Images
代表的なアプリケーション回路