JAJSED9U June 2007 – January 2018 LP3907
PRODUCTION DATA.
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been addressed must generate an acknowledgment (“ACK”) after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W).
NOTE
According to industry I2C standards for 7-bit addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.
The LP3907 has factory-programmed I2C addresses. The WQFN chip has a chip address of 60'h, while the DSBGA chip has a chip address of 61'h.
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform.