JAJSGN6A December   2019  – August 2021 LP875701-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 Multi-Phase DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Multiphase Switcher Configurations
        3. 7.3.1.3 Buck Converter Load-Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1.       53
        2. 7.6.1.1  DEV_REV
        3. 7.6.1.2  OTP_REV
        4. 7.6.1.3  BUCK0_CTRL1
        5. 7.6.1.4  BUCK0_DELAY
        6. 7.6.1.5  GPIO2_DELAY
        7. 7.6.1.6  GPIO3_DELAY
        8. 7.6.1.7  RESET
        9. 7.6.1.8  CONFIG
        10. 7.6.1.9  INT_TOP1
        11. 7.6.1.10 INT_TOP2
        12. 7.6.1.11 INT_BUCK_0_1
        13. 7.6.1.12 INT_BUCK_2_3
        14. 7.6.1.13 TOP_STAT
        15. 7.6.1.14 BUCK_0_1_STAT
        16. 7.6.1.15 BUCK_2_3_STAT
        17. 7.6.1.16 TOP_MASK1
        18. 7.6.1.17 TOP_MASK2
        19. 7.6.1.18 BUCK_0_1_MASK
        20. 7.6.1.19 BUCK_2_3_MASK
        21. 7.6.1.20 SEL_I_LOAD
        22. 7.6.1.21 I_LOAD_2
        23. 7.6.1.22 I_LOAD_1
        24. 7.6.1.23 PGOOD_CTRL1
        25. 7.6.1.24 PGOOD_CTRL2
        26. 7.6.1.25 PGOOD_FLT
        27. 7.6.1.26 PLL_CTRL
        28. 7.6.1.27 PIN_FUNCTION
        29. 7.6.1.28 GPIO_CONFIG
        30. 7.6.1.29 GPIO_IN
        31. 7.6.1.30 GPIO_OUT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Input Capacitor Selection
        3. 8.2.1.3 Output Capacitor Selection
        4. 8.2.1.4 Snubber Components
        5. 8.2.1.5 Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Table 7-9 Summary of LP875701-Q1 Control Registers
AddressRegisterAccessD7D6D5D4D3D2D1D0
0x00DEV_REVRDEVICE_ID[1:0]ALL_LAYER[1:0]METAL_LAYER[3:0]
0x01OTP_REVROTP_ID[7:0]
0x02BUCK0_CTRL1R/WEN_BUCK0EN_PIN_CTRL0BUCK0_EN_PINSELECT[1:0]Reserved - do not useEN_RDIS0Reserved - Do not useReserved - Do not use
0x03Reserved - Do not useRWReserved - Do not use
0x04Reserved - Do not useRWReserved - Do not use
0x05Reserved - Do not useRWReserved - Do not use
0x06Reserved - Do not useRWReserved - Do not use
0x07Reserved - Do not useRWReserved - Do not use
0x08Reserved - Do not useRWReserved - Do not use
0x09Reserved - Do not useRWReserved - Do not use
0x0AReserved - Do not useRWReserved - Do not use
0x0BReserved - Do not useRWReserved - Do not use
0x0CReserved - Do not useRWReserved - Do not use
0x0DReserved - Do not useRWReserved - Do not use
0x0EReserved - Do not useRWReserved - Do not use
0x0FReserved - Do not useRWReserved - Do not use
0x10Reserved - Do not useRWReserved - Do not use
0x11Reserved - Do not useRWReserved - Do not use
0x12BUCK0_DELAYR/WBUCK0_SHUTDOWN_DELAY[3:0]BUCK0_STARTUP_DELAY[3:0]
0x13Reserved - Do not useRWReserved - Do not use
0x14Reserved - Do not useRWReserved - Do not use
0x15Reserved - Do not useRWReserved - Do not use
0x16GPIO2_DELAYR/WGPIO2_SHUTDOWN_DELAY[3:0]GPIO2_STARTUP_DELAY[3:0]
0x17GPIO3_DELAYR/WGPIO3_SHUTDOWN_DELAY[3:0]GPIO3_STARTUP_DELAY[3:0]
0x18RESETR/WReservedSW_RESET
0x19CONFIGR/WDOUBLE_DELAYCLKIN_PDReservedEN3_PDTDIE_WARN_LEVELEN2_PDEN1_PDReserved
0x1AINT_TOP1R/WReservedINT_BUCK23INT_BUCK01NO_SYNC_CLKTDIE_SDTDIE_WARNINT_OVPI_LOAD_READY
0x1BINT_TOP2R/WReservedRESET_REG
0x1CINT_BUCK_0_1R/WReservedBUCK1_PG_INTBUCK1_SC_INTBUCK1_ILIM_INTReservedBUCK0_PG_INTBUCK0_SC_INTBUCK0_ILIM_INT
0x1DINT_BUCK_2_3R/WReservedBUCK3_PG_INTBUCK3_SC_INTBUCK3_ILIM_INTReservedBUCK2_PG_INTBUCK2_SC_INTBUCK2_ILIM_INT
0x1ETOP_STATRReservedSYNC_CLK_STATTDIE_SD_STATTDIE_WARN_STATOVP_STATReserved
0x1FBUCK_0_1_STATRBUCK1_STATBUCK1_PG_STATReservedBUCK1_ILIM_STATBUCK0_STATBUCK0_PG_STATReservedBUCK0_ILIM_STAT
0x20BUCK_2_3_STATRBUCK3_STATBUCK3_PG_STATReservedBUCK3_ILIM_STATBUCK2_STATBUCK2_PG_STATReservedBUCK2_ILIM_STAT
0x21TOP_MASK1R/WReservedReservedSYNC_CLK_MASKReservedTDIE_WARN_MASKReservedI_LOAD_READY_MASK
0x22TOP_MASK2R/WReservedRESET_REG_MASK
0x23BUCK_0_1_MASKR/WReservedBUCK1_PG_MASKReservedBUCK1_ILIM_MASKReservedBUCK0_PG_MASKReservedBUCK0_ILIM_MASK
0x24BUCK_2_3_MASKR/WReservedBUCK3_PG_MASKReservedBUCK3_ILIM_MASKReservedBUCK2_PG_MASKReservedBUCK2_ILIM_MASK
0x25SEL_I_LOADR/WReservedLOAD_CURRENT_BUCK_SELECT[1:0]
0x26I_LOAD_2RReservedBUCK_LOAD_CURRENT[9:8]
0x27I_LOAD_1RBUCK_LOAD_CURRENT[7:0]
0x28PGOOD_CTRL1R/WPG3_SEL[1:0]PG2_SEL[1:0]PG1_SEL[1:0]PG0_SEL[1:0]
0x29PGOOD_CTRL2R/WHALF_DELAYEN_PG0_NINTPGOOD_SET_DELAYEN_PGFLT_STATReservedPGOOD_WINDOWPGOOD_ODPGOOD_POL
0x2APGOOD_FLTRPG3_FLTPG2_FLTPG1_FLTPG0_FLT
0x2BPLL_CTRLR/WPLL_MODE[1:0]ReservedEXT_CLK_FREQ[4:0]
0x2CPIN_FUNCTIONR/WEN_SPREAD_SPECEN_PIN_CTRL_GPIO3EN_PIN_SELECT_GPIO3EN_PIN_CTRL_GPIO2EN_PIN_SELECT_GPIO2GPIO3_SELGPIO2_SELGPIO1_SEL
0x2DGPIO_CONFIGR/WReservedGPIO3_ODGPIO2_ODGPIO1_ODReservedGPIO3_DIRGPIO2_DIRGPIO1_DIR
0x2EGPIO_INRReservedGPIO3_INGPIO2_INGPIO1_IN
0x2FGPIO_OUTR/WReservedGPIO3_OUTGPIO2_OUTGPIO1_OUT

Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for access types in this section.

Table 7-10 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCRRead
R-0RRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value
XValue is set by OTP memory