JAJSNT0A december   2022  – april 2023 MCT8315A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Under Voltage Protection
        7. 7.3.3.7 Buck Over Current Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Speed Control
        1. 7.3.8.1 Analog Mode Speed Control
        2. 7.3.8.2 PWM Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency Mode Speed Control
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 120o Commutation
          1. 7.3.11.1.1 High-Side Modulation
          2. 7.3.11.1.2 Low-Side Modulation
          3. 7.3.11.1.3 Mixed Modulation
        2. 7.3.11.2 Variable Commutation
        3. 7.3.11.3 Lead Angle Control
        4. 7.3.11.4 Closed loop accelerate
      12. 7.3.12 Speed Loop
      13. 7.3.13 Input Power Regulation
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Fast Start-up (< 50 ms)
        1. 7.3.16.1 BEMF Threshold
        2. 7.3.16.2 Dynamic Degauss
      17. 7.3.17 Fast Deceleration
      18. 7.3.18 Active Demagnetization
        1. 7.3.18.1 Active Demagnetization in action
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 Protections
        1. 7.3.21.1  VM Supply Undervoltage Lockout
        2. 7.3.21.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.21.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.21.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.21.5  Overvoltage Protection (OVP)
        6. 7.3.21.6  Overcurrent Protection (OCP)
          1. 7.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.21.7  Buck Overcurrent Protection
        8. 7.3.21.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 7.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 7.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 7.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 7.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 7.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 7.3.21.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.21.10 Thermal Warning (OTW)
        11. 7.3.21.11 Thermal Shutdown (TSD)
        12. 7.3.21.12 Motor Lock (MTR_LCK)
          1. 7.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 7.3.21.13 Motor Lock Detection
          1. 7.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 7.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 7.3.21.14 SW VM Undervoltage Protection
        15. 7.3.21.15 SW VM Overvoltage Protection
        16. 7.3.21.16 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Gate_Driver_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Algo_Control Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 120o and variable commutation
        3. 8.2.1.3 Faster startup time
        4. 8.2.1.4 Setting the BEMF threshold
        5. 8.2.1.5 Maximum speed
        6. 8.2.1.6 Faster deceleration
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 サポート・リソース
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.1 Algorithm_Configuration Registers

Table 7-10 lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses not listed in Table 7-10 should be considered as reserved locations and the register contents should not be modified.

Table 7-10 ALGORITHM_CONFIGURATION Registers
OffsetAcronymRegister NameSection
80hISD_CONFIGISD configurationISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]
82hMOTOR_STARTUP1Motor start-up configuration 1MOTOR_STARTUP1 Register (Offset = 82h) [Reset = 00000000h]
84hMOTOR_STARTUP2Motor start-up configuration 2MOTOR_STARTUP2 Register (Offset = 84h) [Reset = X]
86hCLOSED_LOOP1Closed loop configuration 1CLOSED_LOOP1 Register (Offset = 86h) [Reset = 00000000h]
88hCLOSED_LOOP2Closed loop configuration 2CLOSED_LOOP2 Register (Offset = 88h) [Reset = 00000000h]
8AhCLOSED_LOOP3Closed loop configuration 3CLOSED_LOOP3 Register (Offset = 8Ah) [Reset = 14000000h]
8ChCLOSED_LOOP4Closed loop configuration 4CLOSED_LOOP4 Register (Offset = 8Ch) [Reset = 00000000h]
8EhCONST_SPEEDConstant speed configurationCONST_SPEED Register (Offset = 8Eh) [Reset = 00000000h]
90hCONST_PWRConstant power configurationCONST_PWR Register (Offset = 90h) [Reset = 00000000h]
96h150_DEG_TWO_PH_PROFILE150° Two-ph profile150_DEG_TWO_PH_PROFILE Register (Offset = 96h) [Reset = 00000000h]
98h150_DEG_THREE_PH_PROFILE150° Three-ph profile150_DEG_THREE_PH_PROFILE Register (Offset = 98h) [Reset = 00000000h]
9AhTRAP_CONFIG1Trap configuration 1TRAP_CONFIG1 Register (Offset = 9Ah) [Reset = 00000000h]
9ChTRAP_CONFIG2Trap configuration 2TRAP_CONFIG2 Register (Offset = 9Ch) [Reset = 00200000h]

Complex bit access types are encoded to fit into small table cells. Table 7-11 shows the codes that are used for access types in this section.

Table 7-11 Algorithm_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.7.1.1 ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in Figure 7-56 and described in Table 7-12.

Return to the Summary Table.

Register to configure initial speed detect settings

Figure 7-56 ISD_CONFIG Register
3130292827262524
PARITYISD_ENBRAKE_ENHIZ_ENRVS_DR_ENRESYNC_ENSTAT_BRK_ENSTAT_DETECT_THR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
STAT_DETECT_THRBRK_MODERESERVEDRESERVEDBRK_TIME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BRK_TIMEHIZ_TIMESTARTUP_BRK_TIME
R/W-0hR/W-0hR/W-0h
76543210
STARTUP_BRK_TIMERESYNC_MIN_THRESHOLDRESERVED
R/W-0hR/W-0hR/W-0h
Table 7-12 ISD_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30ISD_ENR/W0h ISD enable
0h = Disable
1h = Enable
29BRAKE_ENR/W0h Brake enable
0h = Disable
1h = Enable
28HIZ_ENR/W0h Hi-Z enable
0h = Disable
1h = Enable
27RVS_DR_ENR/W0h Reverse drive enable
0h = Disable
1h = Enable
26RESYNC_ENR/W0h Resynchronization enable
0h = Disable
1h = Enable
25STAT_BRK_ENR/W0h Enable or disable brake during stationary
0h = Disable
1h = Enable
24-22STAT_DETECT_THRR/W0h Stationary BEMF detect threshold
0h = 5 mV
1h = 10 mV
2h = 15 mV
3h = 20 mV
4h = 25 mV
5h = 30 mV
6h = 50 mV
7h = 100 mV
21BRK_MODER/W0h Brake mode
0h = All three low-side FETs turned ON
1h = All three high-side FETs turned ON
20RESERVEDR/W0h Reserved
19-17RESERVEDR/W0h Reserved
16-13BRK_TIMER/W0h Brake time
0h = 10 ms
1h = 50 ms
2h = 100 ms
3h = 200 ms
4h = 300 ms
5h = 400 ms
6h = 500 ms
7h = 750 ms
8h = 1 s
9h = 2 s
Ah = 3 s
Bh = 4 s
Ch = 5 s
Dh = 7.5 s
Eh = 10 s
Fh = 15 s
12-9HIZ_TIMER/W0h Hi-Z time
0h = 10 ms
1h = 50 ms
2h = 100 ms
3h = 200 ms
4h = 300 ms
5h = 400 ms
6h = 500 ms
7h = 750 ms
8h = 1 s
9h = 2 s
Ah = 3 s
Bh = 4 s
Ch = 5 s
Dh = 7.5 s
Eh = 10 s
Fh = 15 s
8-6STARTUP_BRK_TIMER/W0h Brake time when motor is stationary
0h = 1 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 250 ms
6h = 500 ms
7h = 1000 ms
5-3RESYNC_MIN_THRESHOLDR/W0h Minimum phase BEMF below which the motor is coasted instead of resync
0h = computed based on MIN_DUTY
1h = 300 mV
2h = 400 mV
3h = 500 mV
4h = 600 mV
5h = 800 mV
6h = 1000 mV
7h = 1250 mV
2-0RESERVEDR/W0h Reserved

7.7.1.2 MOTOR_STARTUP1 Register (Offset = 82h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in Figure 7-57 and described in Table 7-13.

Return to the Summary Table.

Register to configure motor startup settings1

Figure 7-57 MOTOR_STARTUP1 Register
3130292827262524
PARITYMTR_STARTUPALIGN_RAMP_RATEALIGN_TIME
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ALIGN_TIMEALIGN_CURR_THRIPD_CLK_FREQ
R/W-0hR/W-0hR/W-0h
15141312111098
IPD_CLK_FREQIPD_CURR_THRIPD_RLS_MODE
R/W-0hR/W-0hR/W-0h
76543210
IPD_ADV_ANGLEIPD_REPEATSLOW_FIRST_CYC_FREQ
R/W-0hR/W-0hR/W-0h
Table 7-13 MOTOR_STARTUP1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29MTR_STARTUPR/W0h Motor start-up method
0h = Align
1h = Double Align
2h = IPD
3h = Slow first cycle
28-25ALIGN_RAMP_RATER/W0h Align voltage ramp rate
0h = 0.1 V/s
1h = 0.2 V/s
2h = 0.5 V/s
3h = 1 V/s
4h = 2.5 V/s
5h = 5 V/s
6h = 7.5 V/s
7h = 10 V/s
8h = 25 V/s
9h = 50 V/s
Ah = 75 V/s
Bh = 100 V/s
Ch = 250 V/s
Dh = 500 V/s
Eh = 750 V/s
Fh = 1000 V/s
24-21ALIGN_TIMER/W0h Align time
0h = 5 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 75 ms
5h = 100 ms
6h = 200 ms
7h = 400 ms
8h = 600 ms
9h = 800 ms
Ah = 1 s
Bh = 2 s
Ch = 4 s
Dh = 6 s
Eh = 8 s
Fh = 10 s
20-17ALIGN_CURR_THRR/W0h Align current threshold (Align current threshold (A) = ALIGN_CURR_THR / CSA_GAIN)
0h = Reserved
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
16-14IPD_CLK_FREQR/W0h IPD clock frequency
0h = 50 Hz
1h = 100 Hz
2h = 250 Hz
3h = 500 Hz
4h = 1000 Hz
5h = 2000 Hz
6h = 5000 Hz
7h = 10000 Hz
13-10IPD_CURR_THRR/W0h IPD current threshold (IPD current threshold (A) = IPD_CURR_THR / CSA_GAIN)
0h = Reserved
1h = Reserved
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
9-8IPD_RLS_MODER/W0h IPD release mode
0h = Brake
1h = Tristate
2h = Reserved
3h = Reserved
7-6IPD_ADV_ANGLER/W0h IPD advance angle
0h = 0°
1h = 30°
2h = 60°
3h = 90°
5-4IPD_REPEATR/W0h Number of times IPD is executed
0h = one
1h = average of 2 times
2h = average of 3 times
3h = average of 4 times
3-0SLOW_FIRST_CYC_FREQR/W0h Frequency of first cycle
0h = 0.05 Hz
1h = 0.1 Hz
2h = 0.25 Hz
3h = 0.5 Hz
4h = 1 Hz
5h = 2 Hz
6h = 3 Hz
7h = 5 Hz
8h = 10 Hz
9h = 15 Hz
Bh = 25 Hz
Ch = 50 Hz
Dh = 100 Hz
Eh = 150 Hz
Fh = 200 Hz

7.7.1.3 MOTOR_STARTUP2 Register (Offset = 84h) [Reset = X]

MOTOR_STARTUP2 is shown in Figure 7-58 and described in Table 7-14.

Return to the Summary Table.

Register to configure motor startup settings2

Figure 7-58 MOTOR_STARTUP2 Register
3130292827262524
PARITYOL_ILIMIT_CONFIGOL_DUTYOL_ILIMIT
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
OL_ILIMITOL_ACC_A1OL_ACC_A2
R/W-0hR/W-0hR/W-0h
15141312111098
OL_ACC_A2OPN_CL_HANDOFF_THR
R/W-0hR/W-0h
76543210
AUTO_HANDOFFFIRST_CYCLE_FREQ_SELMIN_DUTYRESERVED
R/W-0hR/W-0hR/W-0hR-X
Table 7-14 MOTOR_STARTUP2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30OL_ILIMIT_CONFIGR/W0h Open loop current limit configuration
0h = Open loop current limit defined by OL_ILIMIT
1h = Open loop current limit defined by ILIMIT
29-27OL_DUTYR/W0h Duty cycle limit during open loop
0h = 10%
1h = 15%
2h = 20%
3h = 25%
4h = 30%
5h = 40%
6h = 50%
7h = 100%
26-23OL_ILIMITR/W0h Open loop current limit (OL current threshold (A) = OL_CURR_THR / CSA_GAIN)
0h = Reserved
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
22-18OL_ACC_A1R/W0h Open loop acceleration A1
0h = 0.005 Hz/s
1h = 0.01 Hz/s
2h = 0.025 Hz/s
3h = 0.05 Hz/s
4h = 0.1 Hz/s
5h = 0.25 Hz/s
6h = 0.5 Hz/s
7h = 1 Hz/s
8h = 2.5 Hz/s
9h = 5 Hz/s
Ah = 7.5 Hz/s
Bh = 10 Hz/s
Ch = 12.5 Hz/s
Dh = 15 Hz/s
Eh = 20 Hz/s
Fh = 30 Hz/s
10h = 40 Hz/s
11h = 50 Hz/s
12h = 60 Hz/s
13h = 75 Hz/s
14h = 100 Hz/s
15h = 125 Hz/s
16h = 150 Hz/s
17h = 175 Hz/s
18h = 200 Hz/s
19h = 250 Hz/s
1Ah = 300 Hz/s
1Bh = 400 Hz/s
1Ch = 500 Hz/s
1Dh = 750 Hz/s
1Eh = 1000 Hz/s
1Fh = No Limit (32767) Hz/s
17-13OL_ACC_A2R/W0h Open loop acceleration A2
0h = 0.005 Hz/s2
1h = 0.01 Hz/s2
2h = 0.025 Hz/s2
3h = 0.05 Hz/s2
4h = 0.1 Hz/s2
5h = 0.25 Hz/s2
6h = 0.5 Hz/s2
7h = 1 Hz/s2
8h = 2.5 Hz/s2
9h = 5 Hz/s2
Ah = 7.5 Hz/s2
Bh = 10 Hz/s2
Ch = 12.5 Hz/s2
Dh = 15 Hz/s2
Eh = 20 Hz/s2
Fh = 30 Hz/s2
10h = 40 Hz/s2
11h = 50 Hz/s2
12h = 60 Hz/s2
13h = 75 Hz/s2
14h = 100 Hz/s2
15h = 125 Hz/s2
16h = 150 Hz/s2
17h = 175 Hz/s2
18h = 200 Hz/s2
19h = 250 Hz/s2
1Ah = 300 Hz/s2
1Bh = 400 Hz/s2
1Ch = 500 Hz/s2
1Dh = 750 Hz/s2
1Eh = 1000 Hz/s2
1Fh = No Limit (32767) Hz/s2
12-8OPN_CL_HANDOFF_THRR/W0h Open to closed loop handoff threshold
0h = 1 Hz
1h = 4 Hz
2h = 8 Hz
3h = 12 Hz
4h = 16 Hz
5h = 20 Hz
6h = 24 Hz
7h = 28 Hz
8h = 32 Hz
9h = 36 Hz
Ah = 40 Hz
Bh = 45 Hz
Ch = 50 Hz
Dh = 55 Hz
Eh = 60 Hz
Fh = 65 Hz
10h = 70 Hz
11h = 75 Hz
12h = 80 Hz
13h = 85 Hz
14h = 90 Hz
15h = 100 Hz
16h = 150 Hz
17h = 200 Hz
18h = 250 Hz
19h = 300 Hz
1Ah = 350 Hz
1Bh = 400 Hz
1Ch = 450 Hz
1Dh = 500 Hz
1Eh = 550 Hz
1Fh = 600 Hz
7AUTO_HANDOFFR/W0h Auto handoff enable
0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR)
1h = Enable Auto Handoff
6FIRST_CYCLE_FREQ_SELR/W0h First cycle frequency select
0h = Defined by SLOW_FIRST_CYC_FREQ
1h = 0 Hz
5-2MIN_DUTYR/W0h Min operational duty cycle
0h = 1.5 %
1h = 2 %
2h = 3 %
3h = 4 %
4h = 5 %
5h = 6 %
6h = 7 %
7h = 8 %
8h = 9 %
9h = 10 %
Ah = 12 %
Bh = 15 %
Ch = 17.5 %
Dh = 20 %
Eh = 25 %
Fh = 30 %
1-0RESERVEDRX Reserved

7.7.1.4 CLOSED_LOOP1 Register (Offset = 86h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in Figure 7-59 and described in Table 7-15.

Return to the Summary Table.

Register to configure close loop settings1

Figure 7-59 CLOSED_LOOP1 Register
3130292827262524
PARITYCOMM_CONTROLCL_ACC
R/W-0hR/W-0hR/W-0h
2322212019181716
CL_DEC_CONFIGCL_DECPWM_FREQ_OUT
R/W-0hR/W-0hR/W-0h
15141312111098
PWM_FREQ_OUTPWM_MODULPWM_MODELD_ANGLE_POLARITYLD_ANGLE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
LD_ANGLERESERVED
R/W-0hR/W-0h
Table 7-15 CLOSED_LOOP1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29COMM_CONTROLR/W0h Trapezoidal commutation mode
0h = 120° Commutation
1h = Variable commutation between 120° and 150°
2h = Reserved
3h = Reserved
28-24CL_ACCR/W0h Closed loop acceleration rate
0h = 0.005 V/s
1h = 0.01 V/s
2h = 0.025 V/s
3h = 0.05 V/s
4h = 0.1 V/s
5h = 0.25 V/s
6h = 0.5 V/s
7h = 1 V/s
8h = 2.5 V/s
9h = 5 V/s
Ah = 7.5 V/s
Bh = 10 V/s
Ch = 12.5 V/s
Dh = 15 V/s
Eh = 20 V/s
Fh = 30 V/s
10h = 40 V/s
11h = 50 V/s
12h = 60 V/s
13h = 75 V/s
14h = 100 V/s
15h = 125 V/s
16h = 150 V/s
17h = 175 V/s
18h = 200 V/s
19h = 250 V/s
1Ah = 300 V/s
1Bh = 400 V/s
1Ch = 500 V/s
1Dh = 750 V/s
1Eh = 1000 V/s
1Fh = 32767 V/s
23CL_DEC_CONFIGR/W0h Closed loop decel configuration
0h = Close loop deceleration defined by CL_DEC
1h = Close loop deceleration defined by CL_ACC
22-18CL_DECR/W0h Closed loop deceleration rate
0h = 0.005 V/s
1h = 0.01 V/s
2h = 0.025 V/s
3h = 0.05 V/s
4h = 0.1 V/s
5h = 0.25 V/s
6h = 0.5 V/s
7h = 1 V/s
8h = 2.5 V/s
9h = 5 V/s
Ah = 7.5 V/s
Bh = 10 V/s
Ch = 12.5 V/s
Dh = 15 V/s
Eh = 20 V/s
Fh = 30 V/s
10h = 40 V/s
11h = 50 V/s
12h = 60 V/s
13h = 75 V/s
14h = 100 V/s
15h = 125 V/s
16h = 150 V/s
17h = 175 V/s
18h = 200 V/s
19h = 250 V/s
1Ah = 300 V/s
1Bh = 400 V/s
1Ch = 500 V/s
1Dh = 750 V/s
1Eh = 1000 V/s
1Fh = 32767 V/s
17-13PWM_FREQ_OUTR/W0h Output PWM switching frequency
0h = 5 kHz
1h = 6 kHz
2h = 7 kHz
3h = 8 kHz
4h = 9 kHz
5h = 10 kHz
6h = 11 kHz
7h = 12 kHz
8h = 13 kHz
9h = 14 kHz
Ah = 15 kHz
Bh = 16 kHz
Ch = 17 kHz
Dh = 18 kHz
Eh = 19 kHz
Fh = 20 kHz
10h = 25 kHz
11h = 30 kHz
12h = 35 kHz
13h = 40 kHz
14h = 45 kHz
15h = 50 kHz
16h = 55 kHz
17h = 60 kHz
18h = 65 kHz
19h = 70 kHz
1Ah = 75 kHz
1Bh = 80 kHz
1Ch = 85 kHz
1Dh = 90 kHz
1Eh = 95 kHz
1Fh = 100 kHz
12-11PWM_MODULR/W0h PWM modulation.
0h = High-Side Modulation
1h = Low-Side Modulation
2h = Mixed Modulation
3h = Reserved
10PWM_MODER/W0h PWM mode
0h = Single Ended Mode
1h = Complementary Mode
9LD_ANGLE_POLARITYR/W0h Polarity of applied lead angle
0h = Negative
1h = Positive
8-1LD_ANGLER/W0h Lead Angle {Lead Angle (deg) = LD_ANGLE * 0.12}
0RESERVEDR/W0h Reserved

7.7.1.5 CLOSED_LOOP2 Register (Offset = 88h) [Reset = 00000000h]

CLOSED_LOOP2 is shown in Figure 7-60 and described in Table 7-16.

Return to the Summary Table.

Register to configure close loop settings2

Figure 7-60 CLOSED_LOOP2 Register
3130292827262524
PARITYFG_SELFG_DIV_FACTORRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
FG_BEMF_THRMTR_STOPMTR_STOP_BRK_TIME
R/W-0hR/W-0hR/W-0h
15141312111098
MTR_STOP_BRK_TIMEACT_SPIN_BRK_THRBRAKE_DUTY_THRESHOLD
R/W-0hR/W-0hR/W-0h
76543210
AVS_ENCBC_ILIMITRESERVED
R/W-0hR/W-0hR/W-0h
Table 7-16 CLOSED_LOOP2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29FG_SELR/W0h FG mode select
0h = Output FG in open loop and closed loop
1h = Output FG in only closed loop
2h = Output FG in open loop for the first try.
3h = Reserved
28-25FG_DIV_FACTORR/W0h FG division factor
0h = Divide by 3 (2-pole motor mechanical speed/3)
1h = Divide by 1 (2-pole motor mechanical speed)
2h = Divide by 2 (4-pole motor mechanical speed)
3h = Divide by 3 (6-pole motor mechanical speed)
4h = Divide by 4 (8-pole motor mechanical speed)
5h = Divide by 5 (10-pole motor mechanical speed)
6h = Divide by 6 (12-pole motor mechanical speed)
7h = Divide by 7 (14-pole motor mechanical speed)
8h = Divide by 8 (16-pole motor mechanical speed)
9h = Divide by 9 (18-pole motor mechanical speed)
Ah = Divide by 10 (20-pole motor mechanical speed)
Bh = Divide by 11 (22-pole motor mechanical speed)
Ch = Divide by 12 (24-pole motor mechanical speed)
Dh = Divide by 13 (26-pole motor mechanical speed)
Eh = Divide by 14 (28-pole motor mechanical speed)
Fh = Divide by 15 (30-pole motor mechanical speed)
24RESERVEDR/W0h Reserved
23-21FG_BEMF_THRR/W0h FG output BEMF threshold
0h = +/- 1mV
1h = +/- 2mV
2h = +/- 5mV
3h = +/- 10mV
4h = +/- 20mV
5h = +/- 30mV
6h = Reserved
7h = Reserved
20-18MTR_STOPR/W0h Motor stop method
0h = Hi-z
1h = Recirculation
2h = Low-side braking
3h = High-side braking
4h = Active spin down
5h = Reserved
6h = Reserved
7h = Reserved
17-14MTR_STOP_BRK_TIMER/W0h Brake time during motor stop
0h = 1 ms
1h = 2 ms
2h = 5 ms
3h = 10 ms
4h = 15 ms
5h = 25 ms
6h = 50 ms
7h = 75 ms
8h = 100 ms
9h = 250 ms
Ah = 500 ms
Bh = 1000 ms
Ch = 2500 ms
Dh = 5000 ms
Eh = 10000 ms
Fh = 15000 ms
13-11ACT_SPIN_BRK_THRR/W0h Duty cycle threshold for motor stop using active spin down, low- and high-side braking
0h = Immediate
1h = 50 %
2h = 25 %
3h = 15 %
4h = 10 %
5h = 7.5 %
6h = 5 %
7h = 2.5 %
10-8BRAKE_DUTY_THRESHOLDR/W0h Duty cycle threshold for BRAKE pin based low-side braking
0h = Immediate
1h = 50 %
2h = 25 %
3h = 15 %
4h = 10 %
5h = 7.5 %
6h = 5 %
7h = 2.5 %
7AVS_ENR/W0h AVS enable
0h = Disable
1h = Enable
6-3CBC_ILIMITR/W0h Cycle by Cycle (CBC) current limit (CBC current limit (A) = CBC_ILIMIT / CSA_GAIN)
0h = Reserved
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
2-0RESERVEDR/W0h Reserved

7.7.1.6 CLOSED_LOOP3 Register (Offset = 8Ah) [Reset = 14000000h]

CLOSED_LOOP3 is shown in Figure 7-61 and described in Table 7-17.

Return to the Summary Table.

Register to configure close loop settings3

Figure 7-61 CLOSED_LOOP3 Register
3130292827262524
PARITYDYN_DGS_FILT_COUNTDYN_DGS_UPPER_LIMDYN_DGS_LOWER_LIMINTEG_CYCL_THR_LOW
R/W-0hR/W-0hR/W-2hR/W-2hR/W-0h
2322212019181716
INTEG_CYCL_THR_LOWINTEG_CYCL_THR_HIGHINTEG_DUTY_THR_LOWINTEG_DUTY_THR_HIGHBEMF_THRESHOLD2
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BEMF_THRESHOLD2BEMF_THRESHOLD1
R/W-0hR/W-0h
76543210
BEMF_THRESHOLD1INTEG_ZC_METHODDEGAUSS_MAX_WINDYN_DEGAUSS_EN
R/W-0hR/W-0hR/W-0hR/W-0h
Table 7-17 CLOSED_LOOP3 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29DYN_DGS_FILT_COUNTR/W0h Number of samples needed for dynamic degauss check
0h = 15
1h = 20
2h = 30
3h = 12
28-27DYN_DGS_UPPER_LIMR/W2h Dynamic degauss voltage upper bound
0h = (VM - 0.09) V
1h = (VM - 0.12) V
2h = (VM - 0.15) V
3h = (VM - 0.18) V
26-25DYN_DGS_LOWER_LIMR/W2h Dynamic degauss voltage lower bound
0h = 0.03 V
1h = 0.06 V
2h = 0.09 V
3h = 0.12 V
24-23INTEG_CYCL_THR_LOWR/W0h Number of BEMF samples per 30° below which commutation method switches from integration to ZC
0h = 3
1h = 4
2h = 6
3h = 8
22-21INTEG_CYCL_THR_HIGHR/W0h Number of BEMF samples per 30° above which commutation method switches from ZC to integration
0h = 4
1h = 6
2h = 8
3h = 10
20-19INTEG_DUTY_THR_LOWR/W0h Duty cycle below which commutation method switches from integration to ZC
0h = 12 %
1h = 15 %
2h = 18 %
3h = 20 %
18-17INTEG_DUTY_THR_HIGHR/W0h Duty cycle above which commutation method switches from ZC to integration
0h = 12 %
1h = 15 %
2h = 18 %
3h = 20 %
16-11BEMF_THRESHOLD2R/W0h BEMF threshold for integration based commutation during falling floating phase voltage
0h = 0
1h = 25
2h = 50
3h = 75
4h = 100
5h = 125
6h = 150
7h = 175
8h = 200
9h = 225
Ah = 250
Bh = 275
Ch = 300
Dh = 325
Eh = 350
Fh = 375
10h = 400
11h = 425
12h = 450
13h = 475
14h = 500
15h = 525
16h = 550
17h = 575
18h = 600
19h = 625
1Ah = 650
1Bh = 675
1Ch = 700
1Dh = 725
1Eh = 750
1Fh = 775
20h = 800
21h = 850
22h = 900
23h = 950
24h = 1000
25h = 1050
26h = 1100
27h = 1150
28h = 1200
29h = 1250
2Ah = 1300
2Bh = 1350
2Ch = 1400
2Dh = 1450
2Eh = 1500
2Fh = 1550
30h = 1600
31h = 1700
32h = 1800
33h = 1900
34h = 2000
35h = 2100
36h = 2200
37h = 2300
38h = 2400
39h = 2600
3Ah = 2800
3Bh = 3000
3Ch = 3200
3Dh = 3400
3Eh = 3600
3Fh = 3800
10-5BEMF_THRESHOLD1R/W0h BEMF threshold for integration based commutation during rising floating phase voltage
0h = 0
1h = 25
2h = 50
3h = 75
4h = 100
5h = 125
6h = 150
7h = 175
8h = 200
9h = 225
Ah = 250
Bh = 275
Ch = 300
Dh = 325
Eh = 350
Fh = 375
10h = 400
11h = 425
12h = 450
13h = 475
14h = 500
15h = 525
16h = 550
17h = 575
18h = 600
19h = 625
1Ah = 650
1Bh = 675
1Ch = 700
1Dh = 725
1Eh = 750
1Fh = 775
20h = 800
21h = 850
22h = 900
23h = 950
24h = 1000
25h = 1050
26h = 1100
27h = 1150
28h = 1200
29h = 1250
2Ah = 1300
2Bh = 1350
2Ch = 1400
2Dh = 1450
2Eh = 1500
2Fh = 1550
30h = 1600
31h = 1700
32h = 1800
33h = 1900
34h = 2000
35h = 2100
36h = 2200
37h = 2300
38h = 2400
39h = 2600
3Ah = 2800
3Bh = 3000
3Ch = 3200
3Dh = 3400
3Eh = 3600
3Fh = 3800
4INTEG_ZC_METHODR/W0h Commutation method select
0h = ZC based
1h = Integration based
3-1DEGAUSS_MAX_WINR/W0h Maximum degauss window
0h = 22.5°
1h = 10°
2h = 15°
3h = 18°
4h = 30°
5h = 37.5°
6h = 45°
7h = 60°
0DYN_DEGAUSS_ENR/W0h Dynamic degauss detection
0h = Disable
1h = Enable

7.7.1.7 CLOSED_LOOP4 Register (Offset = 8Ch) [Reset = 00000000h]

CLOSED_LOOP4 is shown in Figure 7-62 and described in Table 7-18.

Return to the Summary Table.

Register to configure close loop settings4

Figure 7-62 CLOSED_LOOP4 Register
3130292827262524
PARITYRESERVED
R/W-0hR/W-0h
2322212019181716
RESERVEDWCOMP_BLANK_ENFAST_DEC_DUTY_WIN
R/W-0hR/W-0hR/W-0h
15141312111098
FAST_DEC_DUTY_THRDYN_BRK_CURR_LOW_LIMDYNAMIC_BRK_CURR
R/W-0hR/W-0hR/W-0h
76543210
FAST_DECEL_ENFAST_DECEL_CURR_LIMFAST_BRK_DELTA
R/W-0hR/W-0hR/W-0h
Table 7-18 CLOSED_LOOP4 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-20RESERVEDR/W0h Reserved
19WCOMP_BLANK_ENR/W0h Enable WCOMP blanking during fast deceleration
0h = Disable
1h = Enable
18-16FAST_DEC_DUTY_WINR/W0h Fast deceleration duty window
0h = 0 %
1h = 2.5 %
2h = 5 %
3h = 7.5 %
4h = 10 %
5h = 15 %
6h = 20 %
7h = 25 %
15-13FAST_DEC_DUTY_THRR/W0h Fast deceleration duty threshold
0h = 100 %
1h = 95 %
2h = 90 %
3h = 85 %
4h = 80 %
5h = 75 %
6h = 70%
7h = 65 %
12-9DYN_BRK_CURR_LOW_LIMR/W0h Fast deceleration dynamic current limit lower threshold (Deceleration current lower threshold (A) = DYN_BRK_CURR_LOW_LIM / CSA_GAIN)
0h = Reserved
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
8DYNAMIC_BRK_CURRR/W0h Enable dynamic decrease in current limit during fast deceleration
0h = Disable
1h = Enable
7FAST_DECEL_ENR/W0h Fast deceleration enable
0h = Disable
1h = Enable
6-3FAST_DECEL_CURR_LIMR/W0h Deceleration current threshold (Fast Deceleration current limit upper threshold (A) = FAST_DECEL_CURR_LIM / CSA_GAIN)
0h = Reserved
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
2-0FAST_BRK_DELTAR/W0h Fast deceleration exit speed delta
0h = 0.5 %
1h = 1 %
2h = 1.5 %
3h = 2 %
4h = 2.5 %
5h = 3 %
6h = 4 %
7h = 5 %

7.7.1.8 CONST_SPEED Register (Offset = 8Eh) [Reset = 00000000h]

CONST_SPEED is shown in Figure 7-63 and described in Table 7-19.

Return to the Summary Table.

Register to configure Constant speed mode settings

Figure 7-63 CONST_SPEED Register
3130292827262524
PARITYRESERVEDSPD_POWER_KP
R/W-0hR/W-0hR/W-0h
2322212019181716
SPD_POWER_KPSPD_POWER_KI
R/W-0hR/W-0h
15141312111098
SPD_POWER_KI
R/W-0h
76543210
SPD_POWER_V_MAXSPD_POWER_V_MINCLOSED_LOOP_MODE
R/W-0hR/W-0hR/W-0h
Table 7-19 CONST_SPEED Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30RESERVEDR/W0h Reserved
29-20SPD_POWER_KPR/W0h Speed/ Power loop Kp (Kp = SPD_LOOP_KP / 10000)
19-8SPD_POWER_KIR/W0h Speed/ Power loop Ki (Ki = SPD_LOOP_KI / 1000000)
7-5SPD_POWER_V_MAXR/W0h Upper saturation limit for speed/ power loop
0h = 100 %
1h = 95 %
2h = 90 %
3h = 85 %
4h = 80 %
5h = 75 %
6h = 70%
7h = 65 %
4-2SPD_POWER_V_MINR/W0h Lower saturation limit for speed/power loop
0h = 0 %
1h = 2.5 %
2h = 5 %
3h = 7.5 %
4h = 10 %
5h = 15 %
6h = 20 %
7h = 25 %
1-0CLOSED_LOOP_MODER/W0h Closed loop mode
0h = Disabled
1h = Speed Loop
2h = Power Loop
3h = Reserved

7.7.1.9 CONST_PWR Register (Offset = 90h) [Reset = 00000000h]

CONST_PWR is shown in Figure 7-64 and described in Table 7-20.

Return to the Summary Table.

Register to configure Constant power mode settings

Figure 7-64 CONST_PWR Register
3130292827262524
PARITYMAX_SPEED
R/W-0hR/W-0h
2322212019181716
MAX_SPEED
R/W-0h
15141312111098
MAX_SPEEDDEADTIME_COMP_ENMAX_POWER
R/W-0hR/W-0hR/W-0h
76543210
MAX_POWERCONST_POWER_LIMIT_HYSTCONST_POWER_MODE
R/W-0hR/W-0hR/W-0h
Table 7-20 CONST_PWR Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-15MAX_SPEEDR/W0h Maximum Speed (Maximum Speed (Hz) = MAX_SPEED / 16)
14DEADTIME_COMP_ENR/W0h Enable dead time compensation
0h = Disable
1h = Enable
13-4MAX_POWERR/W0h Maximum power (Maximum power (W) = MAX_POWER / 4)
3-2CONST_POWER_LIMIT_HYSTR/W0h Hysteresis for input power regulation
0h = 5 %
1h = 7.5 %
2h = 10 %
3h = 12.5 %
1-0CONST_POWER_MODER/W0h Input power regulation mode
0h = Disabled
1h = Closed Loop Power Control
2h = Power Limit Control
3h = Reserved

7.7.1.10 150_DEG_TWO_PH_PROFILE Register (Offset = 96h) [Reset = 00000000h]

150_DEG_TWO_PH_PROFILE is shown in Figure 7-65 and described in Table 7-21.

Return to the Summary Table.

Register to configure 150 degree modulation TWO phase duty

Figure 7-65 150_DEG_TWO_PH_PROFILE Register
3130292827262524
PARITYTWOPH_STEP0TWOPH_STEP1TWOPH_STEP2
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TWOPH_STEP2TWOPH_STEP3TWOPH_STEP4
R/W-0hR/W-0hR/W-0h
15141312111098
TWOPH_STEP5TWOPH_STEP6TWOPH_STEP7
R/W-0hR/W-0hR/W-0h
76543210
TWOPH_STEP7RESERVED
R/W-0hR/W-0h
Table 7-21 150_DEG_TWO_PH_PROFILE Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-28TWOPH_STEP0R/W0h 150° modulation , Two ph - step duty - 0
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
27-25TWOPH_STEP1R/W0h 150° modulation , Two ph - step duty - 1
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
24-22TWOPH_STEP2R/W0h 150° modulation, Two ph - step duty - 2
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
21-19TWOPH_STEP3R/W0h 150° modulation, Two ph - step duty - 3
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
18-16TWOPH_STEP4R/W0h 150° modulation, Two ph - step duty - 4
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
15-13TWOPH_STEP5R/W0h 150° modulation, Two ph - step duty - 5
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
12-10TWOPH_STEP6R/W0h 150° modulation, Two ph - step duty - 6
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
9-7TWOPH_STEP7R/W0h 150° modulation, Two ph - step duty - 7
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
6-0RESERVEDR/W0h reserved bits for algo parameter update

7.7.1.11 150_DEG_THREE_PH_PROFILE Register (Offset = 98h) [Reset = 00000000h]

150_DEG_THREE_PH_PROFILE is shown in Figure 7-66 and described in Table 7-22.

Return to the Summary Table.

Register to configure 150 degree modulation Three phase duty

Figure 7-66 150_DEG_THREE_PH_PROFILE Register
3130292827262524
PARITYTHREEPH_STEP0THREEPH_STEP1THREEPH_STEP2
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
THREEPH_STEP2THREEPH_STEP3THREEPH_STEP4
R/W-0hR/W-0hR/W-0h
15141312111098
THREEPH_STEP5THREEPH_STEP6THREEPH_STEP7
R/W-0hR/W-0hR/W-0h
76543210
THREEPH_STEP7LEAD_ANGLE_150DEG_ADVRESERVED
R/W-0hR/W-0hR/W-0h
Table 7-22 150_DEG_THREE_PH_PROFILE Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-28THREEPH_STEP0R/W0h 150° modulation, Three ph - step duty - 0
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
27-25THREEPH_STEP1R/W0h 150° modulation, Three ph - step duty - 1
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
24-22THREEPH_STEP2R/W0h 150° modulation, Three ph - step duty - 2
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
21-19THREEPH_STEP3R/W0h 150° modulation, Three ph - step duty - 3
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
18-16THREEPH_STEP4R/W0h 150° modulation, Three ph - step duty - 4
0h = 0.0 %
1h = 0.5 %
2h = 0.75 %
3h = 0.8375 %
4h = 0.875 %
5h = 0.9375 %
6h = 0.975 %
7h = 0.99 %
15-13THREEPH_STEP5R/W0h 150° modulation, Three ph - step duty - 5
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
12-10THREEPH_STEP6R/W0h 150° modulation, Three ph - step duty - 6
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
9-7THREEPH_STEP7R/W0h 150° modulation, Three ph - step duty - 7
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
6-5LEAD_ANGLE_150DEG_ADVR/W0h Angle advance for 150° modulation
0h = 0°
1h = 5°
2h = 10°
3h = 15°
4-0RESERVEDR/W0h Reserved

7.7.1.12 TRAP_CONFIG1 Register (Offset = 9Ah) [Reset = 00000000h]

TRAP_CONFIG1 is shown in Figure 7-67 and described in Table 7-23.

Return to the Summary Table.

Register to configure internal Algorithm Variables

Figure 7-67 TRAP_CONFIG1 Register
3130292827262524
PARITYRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
OL_HANDOFF_CYCLESRESERVEDAVS_NEG_CURR_LIMIT
R/W-0hR/W-0hR/W-0h
15141312111098
AVS_LIMIT_HYSTISD_BEMF_THRISD_CYCLE_THR
R/W-0hR/W-0hR/W-0h
76543210
ISD_CYCLE_THRRESERVEDRESERVEDZC_ANGLE_OL_THRFAST_STARTUP_DIV_FACTOR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-23 TRAP_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29RESERVEDR/W0h Reserved
28-26RESERVEDR/W0h Reserved
25-24RESERVEDR/W0h Reserved
23-22OL_HANDOFF_CYCLESR/W0h Open loop handoff cycles
0h = 3
1h = 6
2h = 12
3h = 24
21-19RESERVEDR/W0h Reserved
18-16AVS_NEG_CURR_LIMITR/W0h AVS negative current limit (AVS negative current limit (A) = (AVS_NEG_CURRENT_LIMIT * 3 /4095) / CSA_GAIN)
0h = 0
1h = -40
2h = -30
3h = -20
4h = -10
5h = 10
6h = 20
7h = 30
15AVS_LIMIT_HYSTR/W0h AVS current hysteresis (AVS positive current limit (A) = ((AVS_LIMIT_HYST + AVS_NEG_CURR_LIMIT) * 3 /4095) / CSA_GAIN)
0h = 20
1h = 10
14-10ISD_BEMF_THRR/W0h ISD BEMF threshold (ISD BEMF threshold = 200 * ISD_BEMF_THR)
0h = 0
1h = 200
2h = 400
3h = 600
4h = 800
5h = 1000
6h = 1200
7h = 1400
8h = 1600
9h = 1800
Ah = 2000
Bh = 2200
Ch = 2400
Dh = 2600
Eh = 2800
Fh = 3000
10h = 3200
11h = 3400
12h = 3600
13h = 3800
14h = 4000
15h = 4200
16h = 4400
17h = 4600
18h = 4800
19h = 5000
1Ah = 5200
1Bh = 5400
1Ch = 5600
1Dh = 5800
1Eh = 6000
1Fh = 6200
9-7ISD_CYCLE_THRR/W0h ISD cycle threshold
0h = 2,
1h = 5,
2h = 8,
3h = 11,
4h = 14,
5h = 17,
6h = 20,
7h = 23
6RESERVEDR/W0h Reserved
5-4RESERVEDR/W0h Reserved
3-2ZC_ANGLE_OL_THRR/W0h Angle above which the ZC detection is done during OL
0h = 5°
1h = 8°
2h = 12°
3h = 15°
1-0FAST_STARTUP_DIV_FACTORR/W0h Dynamic A1, A2 change rate
0h = 1
1h = 2
2h = 4
3h = 8

7.7.1.13 TRAP_CONFIG2 Register (Offset = 9Ch) [Reset = 00200000h]

TRAP_CONFIG2 is shown in Figure 7-68 and described in Table 7-24.

Return to the Summary Table.

Register to configure internal Algorithm Variables

Figure 7-68 TRAP_CONFIG2 Register
3130292827262524
PARITYTBLANKTPWDTH
R/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDDGS_HIGH_IND_ENRESERVEDALIGN_DUTYZERO_DUTY_HYST
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVED
R/W-0h
Table 7-24 TRAP_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-27TBLANKR/W0h Blanking time after PWM edge
0h = 0 µs
1h = 1 µs
2h = 2 µs
3h = 3 µs
4h = 4 µs
5h = 5 µs
6h = 6 µs
7h = 7 µs
8h = 8 µs
9h = 9 µs
Ah = 10 µs
Bh = 11 µs
Ch = 12 µs
Dh = 13 µs
Eh = 14 µs
Fh = 15 µs
26-24TPWDTHR/W0h Comparator deglitch time
0h = 0 µs
1h = 1 µs
2h = 2 µs
3h = 3 µs
4h = 4 µs
5h = 5 µs
6h = 6 µs
7h = 7 µs
23RESERVEDR/W0h Reserved
22DGS_HIGH_IND_ENR/W0h Degauss Filter for High Inductance Enable
0h = Disable
1h = Enable
21RESERVEDR/W1h Reserved
20-18ALIGN_DUTYR/W0h Duty cycle limit during align
0h = 10 %
1h = 15 %
2h = 20 %
3h = 25 %
4h = 30 %
5h = 40 %
6h = 50 %
7h = 100 %
17-16ZERO_DUTY_HYSTR/W0h Duty cycle hysteresis to exit standby
0h = 0 %
1h = 1 %
2h = 2 %
3h = 3 %
15-0RESERVEDR/W0h Reserved