JAJSDR3D September   2017  – December 2018 OPA2837 , OPA837

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     真のグランド入力および出力範囲を備えた低消費電力、低ノイズ、高精度、シングルエンドSAR ADCドライバ
  3. 3 概要
    1.     Device Images
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: OPA837
    5. 6.5  Thermal Information: OPA2837
    6. 6.6  Electrical Characteristics: VS = 5 V
    7. 6.7  Electrical Characteristics: VS = 3 V
    8. 6.8  Typical Characteristics: VS = 5.0 V
    9. 6.9  Typical Characteristics: VS = 3.0 V
    10. 6.10 Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 OPA837 Comparison
      2. 7.3.2 Input Common-Mode Voltage Range
      3. 7.3.3 Output Voltage Range
      4. 7.3.4 Power-Down Operation
      5. 7.3.5 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      6. 7.3.6 Driving Capacitive Loads
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2 Single-Supply Operation (2.7 V to 5.4 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Noninverting Amplifier
      2. 8.1.2  Inverting Amplifier
      3. 8.1.3  Output DC Error Calculations
      4. 8.1.4  Output Noise Calculations
      5. 8.1.5  Instrumentation Amplifier
      6. 8.1.6  Attenuators
      7. 8.1.7  Differential to Single-Ended Amplifier
      8. 8.1.8  Differential-to-Differential Amplifier
      9. 8.1.9  Pulse Application With Single-Supply Circuit
      10. 8.1.10 ADC Driver Performance
    2. 8.2 Typical Applications
      1. 8.2.1 Active Filters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Implementing a 2:1 Active Multiplexer
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 1-Bit PGA Operation
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

OPA837 DBV Package
6-Pin SOT-23
Top View
OPA837 OPA2837 po_dbv_sbos673.gif
OPA837 DCK Package
5-Pin SC70
Top View
OPA837 OPA2837 po_sot23-5_sbos673.gif
OPA2837 DGK Package
8-Pin VSSOP
Top View
OPA837 OPA2837 pinout-03-DGK-pkg-SBOS673.gif
OPA2837 RUN Package
10-Pin WQFN
Top View
OPA837 OPA2837 pinout-03-RUN-pkg-SBOS673.gif

Pin Functions

PIN FUNCTION(1) DESCRIPTION
NAME OPA837 OPA2837
SOT-23 SC-70 VSSOP WQFN
PD 5 — — — I Amplifier power down.
Low = disabled, high = normal operation (pin must be driven).
PD1 — — — 4 I Amplifier 1 power down.
Low = disabled, high = normal operation (pin must be driven).
PD2 — — — 6 I Amplifier 2 power down.
Low = disabled, high = normal operation (pin must be driven).
VIN– 4 4 — — I Inverting input pin
VIN+ 3 3 — — I Noninverting input pin
VIN1– — — 2 2 I Amplifier 1 inverting input pin
VIN1+ — — 3 3 I Amplifier 1 noninverting input pin
VIN2– — — 6 8 I Amplifier 2 inverting input pin
VIN2+ — — 5 7 I Amplifier 2 noninverting input pin
VOUT 1 1 — — O Output pin
VOUT1 — — 1 1 O Amplifier 1 output pin
VOUT2 — — 7 9 O Amplifier 2 output pin
VS– 2 2 4 5 P Negative power-supply pin
VS+ 6 5 8 10 P Positive power-supply input
(1) I = input, O = output, and P = power.