JAJSLE9 march   2023 OPA928

ADVANCE INFORMATION  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4.     Thermal Information
    5. 6.4 Electrical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Guard Buffer
      2. 7.3.2 Thermal Protection
      3. 7.3.3 Capacitive Load and Stability
      4. 7.3.4 EMI Rejection
      5. 7.3.5 Common-Mode Voltage Range
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Contamination Considerations
      2. 8.1.2 Guarding Considerations
      3. 8.1.3 Humidity Considerations
      4. 8.1.4 Dielectric Relaxation
    2. 8.2 Typical Applications
      1. 8.2.1 High-Impedance (Hi-Z) Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Transimpedance Amplifier
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power-Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
        3. 9.1.1.3 TI のリファレンス・デザイン
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3 Power-Supply Recommendations

The OPA928 is specified for operation from 4.5 V to 16 V (±2.25 V to ±8 V). The OPA928 features a high power-supply rejection ratio (PSRR) and significantly reduces power supply errors at dc. However, a decreasing PSRR at high frequencies means that high-frequency components in the power supply, such as noise, can be coupled to the output. Use a linear, low-noise power supply to optimize noise performance. Place 0.1-μF bypass capacitors close to the power-supply pins to further reduce errors coupling in from the power supplies. For more detailed information on bypass capacitor placement, see Section 8.4. Switching power supplies generate switching noise that can manifest at the output of the OPA928. When switching power supplies cannot be avoided, use proper filtering and a low-dropout regulator to attenuate the switching noise and respective harmonics to an acceptable level.