JAJSLE9A March   2023  – April 2024 OPA928

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: 4.5V ≤ VS < 8V
    6. 5.6 Electrical Characteristics: 8V ≤ VS ≤ 16V
    7. 5.7 Electrical Characteristics: 16V < VS ≤ 36V
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Guard Buffer
      2. 6.3.2 Input Protection
      3. 6.3.3 Thermal Protection
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 EMI Rejection
      6. 6.3.6 Common-Mode Voltage Range
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Contamination Considerations
      2. 7.1.2 Guarding Considerations
      3. 7.1.3 Single-Supply Considerations
      4. 7.1.4 Humidity Considerations
      5. 7.1.5 Dielectric Relaxation
      6. 7.1.6 Shielding
    2. 7.2 Typical Applications
      1. 7.2.1 High-Impedance Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Transimpedance Amplifier
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Input Bias
          2. 7.2.2.2.2 Offset Voltage
          3. 7.2.2.2.3 Stability
          4. 7.2.2.2.4 Noise
      3. 7.2.3 Improved Diode Limiter
      4. 7.2.4 Instrumentation Amplifier
    3. 7.3 Power-Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
        3. 8.1.1.3 TI のリファレンス・デザイン
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Guarding Considerations

This section explores considerations for driving the printed circuit board (PCB) guard with the OPA928 internal guard buffer, an external guard driver, or by connecting the guard copper directly to the analog ground. For details on how to implement a guard in PCB layout, see also Section 7.4.1

Figure 7-1 shows the equivalent schematic of the OPA928 internal guard buffer driving the PCB guard, including the PCB parasitic leakage paths. The guard presents a low-impedance path of near equal potential to the high-impedance input. Parasitic leakage currents that can flow into the high-impedance traces are rerouted through the low-impedance guard. The near equal potential between the input and guard traces makes the current flowing between the two nodes insignificant and the input trace is protected from the undesired leakage current. For a noninverting configuration, the input common-mode voltage changes with the input signal and the guard must be actively driven by a voltage follower that tracks the input signal. The OPA928 features a high-performance internal guard buffer that can be accessed at pin 2 and pin 7 to drive the PCB guard copper; see the Electrical Characteristics for specified guard buffer performance. The internal guard buffer tracks the voltage of the OPA928 input signal and is isolated from capacitive loads through a 1kΩ isolation resistor, RISO.

OPA928 Driving the Guard, Internal
                    Guard Buffer Figure 7-1 Driving the Guard, Internal Guard Buffer

Figure 7-2 shows how the PCB guard is driven with an external guard driver instead of the OPA928 internal guard buffer. To prevent the input bias current of the external guard driver from degrading the input signal, track the low-impedance input of the OPA928. If an external guard driver is used, the OPA928 guard pins can be left unconnected or can be overdriven by the external guard driver. Choose a low-offset, low-noise amplifier for the guard driver because any voltage potential between guard and input traces causes current to leak through the high-impedance trace. Include an isolation resistor at the output of the guard driver to prevent gain peaking due to capacitive loading and to provide short-circuit protection. Confirm that the guard driver is stable and capable of driving the capacitive load presented by the guard, including long cable lengths, if applicable.

OPA928 Driving the Guard, External
                    Guard Driver Figure 7-2 Driving the Guard, External Guard Driver

For inverting configurations, the input common-mode voltage is fixed to the analog ground or some dc reference voltage applied to the noninverting input. In this case, the PCB guard can be tied directly to ground or low-impedance reference of the signal amplifier. Connecting the PCB guard to a low-impedance reference or ground makes sure that the guard potential is always equal to the input common-mode voltage, without the additional offset and noise of an active guard driver. If the PCB guard is connected to the analog ground of the circuit, make sure that current return paths do not cross through the guard area. Keep power and digital grounds separate from the guard and prevent ground loops from occurring.