JAJSQE5
may 2023
SN74LV2T74-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Characteristics 1.8-V VCC
6.7
Timing Characteristics 2.5-V VCC
6.8
Timing Characteristics 3.3-V VCC
6.9
Timing Characteristics 5-V VCC
6.10
Switching Characteristics 1.8-V VCC
6.11
Switching Characteristics 2.5-V VCC
6.12
Switching Characteristics 3.3-V VCC
6.13
Switching Characteristics 5-V VCC
6.14
Noise Characteristics
6.15
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
Clamp Diode Structure
8.3.3
LVxT Enhanced Input Voltage
8.3.3.1
Down Translation
8.3.3.2
Up Translation
8.3.4
Wettable Flanks
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Input Considerations
9.2.1.2
Output Considerations
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
ドキュメントの更新通知を受け取る方法
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PW|14
MPDS360A
BQA|14
MPQF538A
サーマルパッド・メカニカル・データ
BQA|14
QFND687
発注情報
jajsqe5_oa
jajsqe5_pm
11.1
Documentation Support