JAJSQE5 may 2023 SN74LV2T74-Q1
PRODUCTION DATA
Signals can be translated down using the SN74LV2T74-Q1. The voltage applied at the VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables.
When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0 V in the LOW state. As shown in Figure 8-3, ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input signals in the LOW state are lower than VIL(MAX).
As shown in Figure 8-4 for example, the standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to match 1.8 V CMOS signals when operating from 1.8-V VCC.
Down Translation Combinations are as follows: