JAJSJY2B june   2021  – march 2023 TCA39306

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Definition of threshold voltage
      2. 8.1.2 Correct Device Set Up
      3. 8.1.3 Disconnecting a Responder from the Main Bus Using the EN Pin
      4. 8.1.4 Supporting Remote Board Insertion to Backplane with TCA39306
      5. 8.1.5 Switch Configuration
      6. 8.1.6 Controller on Side 1 or Side 2 of Device
      7. 8.1.7 LDO and TCA39306 Concerns
      8. 8.1.8 Current Limiting Resistance on VREF2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable (EN) Pin
      2. 8.3.2 Voltage Translation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Applications of I2C
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bidirectional Voltage Translation
        2. 9.2.2.2 Sizing Pullup Resistors
        3. 9.2.2.3 Bandwidth
      3. 9.2.3 Application Curve
    3. 9.3 Systems Examples: I3C Usage Considerations
      1. 9.3.1 I3C Bus Switching
      2. 9.3.2 I3C Bus Voltage Translation
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.7 LDO and TCA39306 Concerns

The VREF1 pin can be supplied by a low-dropout regulator (LDO), but in some cases the LDO may lose its regulation because of the bias current from VREF2 to VREF1. If the LDO cannot sink the bias current, then the current has no other paths to ground and instead charges up the capacitance on the VREF1 node (both external and parasitic). This results in an increase in voltage on the VREF1 node. If no other paths for current to flow are established (such as back biasing of body diodes or clamping diodes through other devices on the VREF1 node), then the VREF1 voltage ends up stabilizing when Vgs of the pass FET is equal to Vth. This means VREF1 node voltage is VCC2 - Vth.  Note that any secondary or primaries running off of the LDO now see the VCC2 - Vth voltage which may cause damage to those secondary or primaries if they are not rated to handle the increased voltage.

GUID-20210519-CA0I-NH39-K9MS-NVP7PMDZGXKZ-low.svg Figure 8-8 Example of no leakage current path when using LDO

To make sure the LDO does not lose regulation due to the bias current of TCA39306, a weak pull down resistor can be placed on VREF1 to ground to provide a path for the bias current to travel. The recommended pull down resistor is calculated by Equation 4 where 0.75 gives about 25% margin for error incase bias current increases during operation.

GUID-20210519-CA0I-LTMN-DHD1-2VZGMBHX6WJB-low.svg Figure 8-9 Example with Leakage current path when using an LDO
Equation 1. Ven = VREF1 + Vth

where

  • Vth is approximately 0.6 V

Equation 2. Ibias = (VCC2 - Ven)/200 k
Equation 3. Rpulldown = VOUT/Ibias
Equation 4. Recommended Rpulldown = Rpulldown x 0.75