JAJSN80E August   2009  – May 2022 TCA9535


  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1.      Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V Tolerant I/O Ports
      2. 7.3.2 Hardware Address Pins
      3. 7.3.3 Interrupt ( INT) Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Powered-Up
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. Bus Transactions
          1. Writes
          2. Reads
      2. 7.5.2 Device Address
      3. 7.5.3 Control Register and Command Byte
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. Calculating Junction Temperature and Power Dissipation
        2. Minimizing ICC When I/O is Used to Control LED
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



I2C Interface

The TCA9535 has a standard bidirectional I2C interface that is controlled by a controller device in order to be configured or read the status of this device. Each target on the I2C bus has a specific device address to differentiate between other target devices that are on the same I2C bus. Many target devices require configuration upon startup to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. For more information see Understanding the I2C Bus application report, SLVA704.

The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I2C lines. For further details, see I2C Pull-up Resistor Calculation application report, SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. See Table 7-1.

Figure 7-3 and Figure 7-4 show the general procedure for a controller to access a target device:

  1. If a controller wants to send data to a target:
    • Controller-transmitter sends a START condition and addresses the target-receiver.
    • Controller-transmitter sends data to target-receiver.
    • Controller-transmitter terminates the transfer with a STOP condition.
  2. If a controller wants to receive or read data from a target:
    • Controller-receiver sends a START condition and addresses the target-transmitter.
    • Controller-receiver sends the requested register to read to target-transmitter.
    • Controller-receiver receives data from the target-transmitter.
    • Controller-receiver terminates the transfer with a STOP condition.
GUID-0D9F5F59-616C-4460-9564-9ACB37B9EE08-low.gifFigure 7-3 Definition of Start and Stop Conditions
GUID-5267E2A7-E12C-42EE-8836-9905CC1E3E33-low.gifFigure 7-4 Bit Transfer

Table 7-1 shows the interface definition.

Table 7-1 Interface Definition
7 (MSB)6543210 (LSB)
I2C target addressLHLLA2A1A0R/ W
P0x I/O data busP07P06P05P04P03P02P01P00
P1x I/O data busP17P16P15P14P13P12P11P10