JAJSI83G May 2012 – November 2019 TCA9548A
In the event of a glitch or data corruption, TCA9548A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 17.
Table 3 specifies the performance of the power-on reset feature for TCA9548A for both types of power-on reset.
|VCC_FT||Fall time||See Figure 17||1||100||ms|
|VCC_RT||Rise time||See Figure 17||0.1||100||ms|
|VCC_TRR||Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or when VCC drops to GND)||See Figure 17||40||μs|
|VCC_GH||Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 μs||See Figure 18||1.2||V|
|VCC_GW||Glitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC||See Figure 18||10||μs|
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 18 and Table 3 provide more information on how to measure these specifications.
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 19 and Table 3 provide more details on this specification.