JAJSI83G May   2012  – November 2019 TCA9548A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Reset Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 RESET Input
      2. 9.4.2 Power-On Reset
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
      2. 9.5.2 Device Address
      3. 9.5.3 Bus Transactions
        1. 9.5.3.1 Writes
        2. 9.5.3.2 Reads
      4. 9.5.4 Control Register
      5. 9.5.5 RESET Input
      6. 9.5.6 Power-On Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-On Reset Requirements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9548A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

A power-on reset is shown in Figure 17.

TCA9548A pwron02_cps204.gif
VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Figure 17. Power-On Reset Waveform

Table 3 specifies the performance of the power-on reset feature for TCA9548A for both types of power-on reset.

Table 3. Recommended Supply Sequencing and Ramp Rates(1)

PARAMETER MIN MAX UNIT
VCC_FT Fall time See Figure 17 1 100 ms
VCC_RT Rise time See Figure 17 0.1 100 ms
VCC_TRR Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or when VCC drops to GND) See Figure 17 40 μs
VCC_GH Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 μs See Figure 18 1.2 V
VCC_GW Glitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC See Figure 18 10 μs
(1) All supply sequencing and ramp rate values are measured at TA = 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 18 and Table 3 provide more information on how to measure these specifications.

TCA9548A pwron03_cps204.gifFigure 18. Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 19 and Table 3 provide more details on this specification.

TCA9548A pwron04_cps204.gifFigure 19. VPOR