JAJSFY9A December   2017  – August 2018 TLC6C5724-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Constant-Sink-Current Setting
      2. 7.3.2 Brightness Control and Dot Correction
      3. 7.3.3 Grayscale Configuration
        1. 7.3.3.1 PWM Auto Repeat
        2. 7.3.3.2 PWM Timing Reset
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  LED Diagnostics
        2. 7.3.4.2  Adjacent-Pin-Short Check
        3. 7.3.4.3  IREF Short and IREF Open Detection
        4. 7.3.4.4  Pre-Thermal Warning Flag
        5. 7.3.4.5  Thermal Error Flag
        6. 7.3.4.6  Negate Bit Toggle
        7. 7.3.4.7  LOD_LSD Self-Test
        8. 7.3.4.8  ERR Pin
        9. 7.3.4.9  ERROR Clear
        10. 7.3.4.10 Global Reset
        11. 7.3.4.11 Slew Rate Control
        12. 7.3.4.12 Channel Group Delay
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up
      2. 7.4.2 Device Initialization
      3. 7.4.3 Fault Mode
      4. 7.4.4 Normal Operation
    5. 7.5 Programming
      1. 7.5.1 Register Write and Read
        1. 7.5.1.1 FC-BC-DC Write
          1. 7.5.1.1.1 FC Data Write
          2. 7.5.1.1.2 BC Data Write
          3. 7.5.1.1.3 DC Data Write
        2. 7.5.1.2 Grayscale Data Write
        3. 7.5.1.3 Special Command Function
          1. 7.5.1.3.1 GS Read
          2. 7.5.1.3.2 FC-BC-DC Read
          3. 7.5.1.3.3 Status Information Data Read
    6. 7.6 Register Maps
      1. 7.6.1 GRAYSCALE Registers
        1. 7.6.1.1 OUTn_GS Register (Offset = 0h)
          1. Table 25. OUTn_GS Register Field Descriptions
      2. 7.6.2 FC-BC-DC Registers
        1. 7.6.2.1 FC-BC-DC Register (Offset = 1h)
          1. Table 28. FC-BC-DC Register Field Descriptions
      3. 7.6.3 SID Registers
        1. 7.6.3.1 SID Register (Offset = 2h)
          1. Table 31. SID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.1.1 OUTn_GS Register (Offset = 0h)

OUTn_GS is shown in Figure 28 and described in Table 25.

Return to Summary Table.

OUTn Grayscale Register

Figure 28. OUTn_GS Register
287 286 285 284 283 282 281 280 279 278 277 276
OUTB7_GS
R/W-0h
275 274 273 272 271 270 269 268 267 266 265 264
OUTG7_GS
R/W-0h
263 262 261 260 259 258 257 256 255 254 253 252
OUTR7_GS
R/W-0h
251 250 249 248 247 246 245 244 243 242 241 240
OUTB6_GS
R/W-0h
239 238 237 236 235 234 233 232 231 230 229 228
OUTG6_GS
R/W-0h
227 226 225 224 223 222 221 220 219 218 217 216
OUTR6_GS
R/W-0h
215 214 213 212 211 210 209 208 207 206 205 204
OUTB5_GS
R/W-0h
203 202 201 200 199 198 197 196 195 194 193 192
OUTG5_GS
R/W-0h
191 190 189 188 187 186 185 184 183 182 181 180
OUTR5_GS
R/W-0h
179 178 177 176 175 174 173 172 171 170 169 168
OUTB4_GS
R/W-0h
167 166 165 164 163 162 161 160 159 158 157 156
OUTG4_GS
R/W-0h
155 154 153 152 151 150 149 148 147 146 145 144
OUTR4_GS
R/W-0h
143 142 141 140 139 138 137 136 135 134 133 132
OUTB3_GS
R/W-0h
131 130 129 128 127 126 125 124 123 122 121 120
OUTG3_GS
R/W-0h
119 118 117 116 115 114 113 112 111 110 109 108
OUTR3_GS
R/W-0h
107 106 105 104 103 102 101 100 99 98 97 96
OUTB2_GS
R/W-0h
95 94 93 92 91 90 89 88 87 86 85 84
OUTG2_GS
R/W-0h
83 82 81 80 79 78 77 76 75 74 73 72
OUTR2_GS
R/W-0h
71 70 69 68 67 66 65 64 63 62 61 60
OUTB1_GS
R/W-0h
59 58 57 56 55 54 53 52 51 50 49 48
OUTG1_GS
R/W-0h
47 46 45 44 43 42 41 40 39 38 37 36
OUTR1_GS
R/W-0h
35 34 33 32 31 30 29 28 27 26 25 24
OUTB0_GS
R/W-0h
23 22 21 20 19 18 17 16 15 14 13 12
OUTG0_GS
R/W-0h
11 10 9 8 7 6 5 4 3 2 1 0
OUTR0_GS
R/W-0h

Table 25. OUTn_GS Register Field Descriptions

Bit Field Type Default Description
287–276 OUTB7_GS[11:0] R/W 0h

Grayscale register for OUTB7
275–264 OUTG7_GS[11:0] R/W 0h

Grayscale register for OUTG7
263–252 OUTR7_GS[11:0] R/W 0h

Grayscale register for OUTR7
251–240 OUTB6_GS[11:0] R/W 0h

Grayscale register for OUTB6
239–228 OUTG6_GS[11:0] R/W 0h

Grayscale register for OUTG6
227–216 OUTR6_GS[11:0] R/W 0h

Grayscale register for OUTR6
215–204 OUTB5_GS[11:0] R/W 0h

Grayscale register for OUTB5
203–192 OUTG5_GS[11:0] R/W 0h

Grayscale register for OUTG5
191–180 OUTR5_GS[11:0] R/W 0h

Grayscale register for OUTR5
179–168 OUTB4_GS[11:0] R/W 0h

Grayscale register for OUTB4
167–156 OUTG4_GS[11:0] R/W 0h

Grayscale register for OUTG4
155–144 OUTR4_GS[11:0] R/W 0h

Grayscale register for OUTR4
143–132 OUTB3_GS[11:0] R/W 0h

Grayscale register for OUTB3
131–120 OUTG3_GS[11:0] R/W 0h

Grayscale register for OUTG3
119–108 OUTR3_GS[11:0] R/W 0h

Grayscale register for OUTR3
107–96 OUTB2_GS[11:0] R/W 0h

Grayscale register for OUTB2
95–84 OUTG2_GS[11:0] R/W 0h

Grayscale register for OUTG2
83–72 OUTR2_GS[11:0] R/W 0h

Grayscale register for OUTR2
71–60 OUTB1_GS[11:0] R/W 0h

Grayscale register for OUTB1
59–48 OUTG1_GS[11:0] R/W 0h

Grayscale register for OUTG1
47–36 OUTR1_GS[11:0] R/W 0h

Grayscale register for OUTR1
35–24 OUTB0_GS[11:0] R/W 0h

Grayscale register for OUTB0
23–12 OUTG0_GS[11:0] R/W 0h

Grayscale register for OUTG0
11–0 OUTR0_GS[11:0] R/W 0h

Grayscale register for OUTR0