SPNS141G August   2010  – October 2018 TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS20206 , TMS570LS20216

PRODUCTION DATA.  

  1. 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller
    1. 1.1 Features
    2. 1.2 Description
    3. 1.3 Functional Block Diagram
  2. 2 Device Overview
    1. 2.1 Terms and Acronyms
    2. 2.2 Device Characteristics
    3. 2.3 Memory
      1. 2.3.1 Memory Map
      2. 2.3.2 Flash Memory
      3. 2.3.3 System Modules Assignment
      4. 2.3.4 Peripheral Selects
      5. 2.3.5 Memory Auto-Initialization
      6. 2.3.6 PBIST RAM Self Test
    4. 2.4 Pin Assignments
      1. 2.4.1 PGE QFP Package Pinout (144 pin)
      2. 2.4.2 ZWT BGA Package Pinout (337 ball)
    5. 2.5 Terminal Functions
    6. 2.6 Device Support
      1. 2.6.1 Device and Development-Support Tool Nomenclature
  3. 3 Reset / Abort Sources
    1. 3.1 Reset / Abort Sources
  4. 4 Peripherals
    1. 4.1  Error Signaling Module (ESM)
    2. 4.2  Direct Memory Access (DMA)
    3. 4.3  High End Timer Transfer Unit (HET-TU)
    4. 4.4  Vectored Interrupt Manager (VIM)
    5. 4.5  MIBADC Event Trigger Sources
    6. 4.6  MIBSPI
      1. 4.6.1 MIBSPI Event Trigger Sources
      2. 4.6.2 MIBSPIP5/DMM Pin Multiplexing
    7. 4.7  ETM
    8. 4.8  Debug Scan Chains
      1. 4.8.1 JTAG
    9. 4.9  CCM
      1. 4.9.1 Dual Core Implementation
      2. 4.9.2 CCM-R4
    10. 4.10 LPM
    11. 4.11 Voltage Monitor
    12. 4.12 CRC
    13. 4.13 System Module Access
    14. 4.14 Debug ROM
    15. 4.15 CPU Self Test Controller: STC / LBIST
  5. 5 Device Registers
    1. 5.1 Device Identification Code Register
      1. Table 5-1 Device ID Bit Allocation Register Field Descriptions
    2. 5.2 Die-ID Registers
    3. 5.3 PLL Registers
  6. 6 Device Electrical Specifications
    1. 7 Operating Conditions
      1. 7.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
      2. 7.2 Device Recommended Operating Conditions
      3. 7.3 Electrical Characteristics Over Operating Free-Air Temperature Range
  7. 8 Peripheral and Electrical Specifications
    1. 8.1  Clocks
      1. 8.1.1 PLL And Clock Specifications
      2. 8.1.2 External Reference Resonator/Crystal Oscillator Clock Option
      3. 8.1.3 Validated FMPLL Setting
      4. 8.1.4 LPO And Clock Detection
      5. 8.1.5 Switching Characteristics Over Recommended Operating Conditions For Clocks
        1. 8.1.5.1 Timing - Wait States
    2. 8.2  ECLK Specification
      1. 8.2.1 Switching Characteristics Over Recommended Operating Conditions For External Clocks
    3. 8.3  RST And PORRST Timings
      1. 8.3.1 Timing Requirements For PORRST
      2. 8.3.2 Switching Characteristics Over Recommended Operating Conditions For RST
      3. 8.3.3 IO Status During PORRST
    4. 8.4  TEST Pin Timing
    5. 8.5  DAP - JTAG Scan Interface Timing
      1. 8.5.1 JTAG clock specification 12-MHz and 50-pF load on TDO output
    6. 8.6  Output Timings
      1. 8.6.1 Switching Characteristics For Output Timings Versus Load Capacitance (CL)
    7. 8.7  Input Timings
      1. 8.7.1 Timing Requirements For Input Timings
    8. 8.8  Flash Timings
    9. 8.9  SPI Master Mode Timing Parameters
      1. 8.9.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
      2. 8.9.2 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
    10. 8.10 SPI Slave Mode Timing Parameters
      1. 8.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)
      2. 8.10.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)
    11. 8.11 CAN Controller Mode Timings
      1. 8.11.1 Dynamic Characteristics For The CANnTX And CANnRX Pins
    12. 8.12 SCI/LIN Mode Timings
    13. 8.13 FlexRay Controller Mode Timings
      1. 8.13.1 Jitter Timing
    14. 8.14 EMIF Timings
      1. 8.14.1 Read Timing (Asynchronous RAM)
      2. 8.14.2 Write Timing (Asynchronous RAM)
    15. 8.15 ETM Timings
      1. 8.15.1 ETMTRACECLK Timing
      2. 8.15.2 ETMDATA Timing
    16. 8.16 RTP Timings
      1. 8.16.1 RTPCLK Timing
      2. 8.16.2 RTPDATA Timing
      3. 8.16.3 RTPENABLE Timing
    17. 8.17 DMM Timings
      1. 8.17.1 DMMCLK Timing
      2. 8.17.2 DMMDATA Timing
      3. 8.17.3 DMMENA Timing
    18. 8.18 MibADC
      1. 8.18.1 MibADC
      2. 8.18.2 MibADC Recommended Operating Conditions
      3. 8.18.3 Operating Characteristics Over Full Ranges Of Recommended Operating Conditions
      4. 8.18.4 MibADC Input Model
      5. 8.18.5 MibADC Timings
      6. 8.18.6 MibADC Nonlinearity Error
      7. 8.18.7 MibADC Total Error
  8. 9 Revision History
  9. 10Mechanical Packaging and Orderable Information
    1. 10.1 Thermal Data
      1. 10.1.1 PGE (S-PQFP-G144) plastic Quad Flat Pack
      2. 10.1.2 ZWT (S-PBGA-N337) Plastic ball grid array
    2. 10.2 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZWT|337
サーマルパッド・メカニカル・データ
発注情報

4.4 Vectored Interrupt Manager (VIM)

The Vectored Interrupt Manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on the device. Interrupt requests originating from the device modules (i.e., SPI, LIN, SCI, etc.) are assigned to channels within the 64-channel VIM. Programming multiple interrupt sources to the same VIM channel effectively shares the VIM channel between sources. The VIM request channels are maskable so that individual channels can be selectively disabled. All interrupt requests can be programmed in the VIM to be of either type:

  • Fast interrupt request (FIQ)- The FIQ implemented in Cortex-R4F is Non-Maskable Fast Interrupts (NMFI).
  • Normal interrupt request (IRQ)

The VIM prioritizes interrupts, whose precedence of request channels decrease with ascending channel order in the VIM (0 [highest] and 64[lowest] priority). For VIM default mapping, channel priorities, and their associated modules see the table below. More information on the VIM can be found in the technical reference manual (TRM).

Table 4-5 Interrupt Request Assignments

Modules Interrupt Sources Default VIM Interrupt Request
ESM ESM High level interrupt (NMI) 0
Reserved (NMI) 1
RTI RTI compare interrupt 0 2
RTI RTI compare interrupt 1 3
RTI RTI compare interrupt 2 4
RTI RTI compare interrupt 3 5
RTI RTI overflow interrupt 0 6
RTI RTI overflow interrupt 1 7
RTI RTI timebase 8
GIO GIO interrupt A 9
NHET NHET level 1 interrupt 10
HET TU HET TU level 1 interrupt 11
MIBSPI1 MIBSPI1 level 0 interrupt 12
LIN1 (incl. SCI) LIN1 level 0 interrupt 13
MIBADC1 MIBADC1 event group interrupt 14
MIBADC1 MIBADC1 sw group 1 interrupt 15
DCAN1 DCAN1 level 0 interrupt 16
Reserved Reserved 17
FlexRay FlexRay level 0 interrupt 18
CRC CRC Interrupt 19
ESM ESM Low level interrupt 20
SYSTEM Software interrupt (SSI) 21
CPU PMU Interrupt 22
GIO GIO interrupt B 23
NHET NHET level 2 interrupt 24
HET TU HET TU level 2 interrupt 25
MIBSPI1 MIBSPI1 level 1 interrupt 26
LIN1 (incl. SCI) LIN1 level 1 interrupt 27
MIBADC1 MIBADC1 sw group 2 interrupt 28
DCAN1 DCAN1 level 1 interrupt 29
Reserved Reserved 30
MIBADC1 MIBADC1 magnitude interrupt 31
FlexRay FlexRay level 1 interrupt 32
DMA FTCA interrupt 33
DMA LFSA interrupt 34
DCAN2 DCAN2 level 0 interrupt 35
DMM DMM level 0 interrupt 36
MIBSPI3 MIBSPI3 level 0 interrupt 37
MIBSPI3 MIBSPI3 level 1 interrupt 38
DMA HBCA interrupt 39
DMA BTCA interrupt 40
Reserved Reserved 41
DCAN2 DCAN2 level 1 interrupt 42
DMM DMM level 1 interrupt 43
DCAN1 DCAN1 IF3 interrupt 44
DCAN3 DCAN3 level 0 interrupt 45
DCAN2 DCAN2 IF3 interrupt 46
FPU FPU interrupt 47
FlexRay TU FlexRay TU Transfer Status interrupt 48
LIN2 (incl. SCI) LIN2 level 0 interrupt 49
MIBADC2 MIBADC2 event group interrupt 50
MIBADC2 MIBADC2 sw group 1 interrupt 51
FlexRay FlexRay T0C interrupt 52
MIBSPIP5 MIBSPIP5 level 0 interrupt 53
LIN2 (incl. SCI) LIN2 level 1 interrupt 54
DCAN3 DCAN3 level 1 interrupt 55
MIBSPIP5 MIBSPIP5 level 1 interrupt 56
MIBADC2 MIBADC2 sw group 2 interrupt 57
FlexRay TU FlexRay TU Error interrupt 58
MIBADC2 MIBADC2 magnitude interrupt 59
DCAN3 DCAN3 IF3 interrupt 60
Reserved Reserved 61
FlexRay FlexRay T1C interrupt 62
Reserved Reserved 63
Note: Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry.