SLASEW5 December   2020 TMUXHS4412


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable and Power Savings
      2. 7.3.2 Data Line Biasing
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Lane Muxing
        1. Design Requirements
        2. Detailed Design Procedure
        3. Pin-to-pin Passive versus Redriver Option
        4. Application Curves
    3. 8.3 Systems Examples
      1. 8.3.1 PCIe Muxing for Hybrid SSD
      2. 8.3.2 DisplayPort Main Link
      3. 8.3.3 USB 4.0 / TBT 3.0 Demuxing
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



Data Line Biasing

The TMUXHS4412 has a weak pull-down of 1MΩ from D[0/1/2/3][P/N] pins to GND. While these resistors biases the device data channels to common mode voltage (CMV) of 0 V with very weak strength, it is recommended that the device is biased by a stronger impedance from either side of the device to a valid value. To avoid double biasing appropriate AC coupling capacitors should be ensured on either side of the device.

In certain use cases if both side of the TMUXHS4412 is ac coupled, it is recommended that appropriate CMV biasing is used for the device. 10 kΩ to GND or any other bias voltage in the CMV range for each D[0/1/2/3][P/N] pin will suffice for most use cases.

The high-speed data ports incorporate 20 kΩ pull-down resistors that are switched in when a port is not selected and switched out when the port is selected. For example when SEL = L, the DB[0/1/2/3][P/N] pins have 20 kΩ resistors to GND. The feature ensures that unselected port is always biased to a known voltage for long term reliability of the device and the electrical channel.

The positive and negative terminals of data pins D[0/1/2/3] have a weak (20 kΩ) differential resistor in between them for device switch regulation operation. This does not impact signal integrity or functionality of high speed differential signaling that typically has much stronger differential impedance (such as 100 Ω).