SLVSCH2 July   2014 TPS2105-EP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1. 5.1 Function Table
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Switches
        1. 7.3.1.1 N-Channel MOSFET
        2. 7.3.1.2 P-Channel MOSFET
        3. 7.3.1.3 Charge Pump
        4. 7.3.1.4 Driver
        5. 7.3.1.5 Enable
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With EN Control
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step-by-Step Design Procedure
        2. 8.2.2.2 Power-Supply Considerations
        3. 8.2.2.3 Switch Transition
        4. 8.2.2.4 Thermal Protection
        5. 8.2.2.5 Undervoltage Lockout
        6. 8.2.2.6 Power Dissipation and Junction Temperature
        7. 8.2.2.7 ESD Protection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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発注情報

8 Application and Implementation

8.1 Application Information

The TPS2105 is a dual-input, single-output power switch designed to provide uninterrupted output voltage when transitioning between two independent power supplies.

8.2 Typical Application

typapp_figure19_slvsch2.gifFigure 15. Typical Application Schematic

8.2.1 Design Requirements

For this design example, use the following as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range, VI(IN1) 5 V
Input voltage range, VI(IN2) 5 V
Output voltage 5 V
Continuous output current, IO 100 mA
Output capacitor, CL 220 µF

8.2.2 Detailed Design Procedure

8.2.2.1 Step-by-Step Design Procedure

To begin the design process, the designer must decide upon a few parameters. The designer needs to know the following:

  • Input voltage range, VI(IN1)
  • Input voltage range, VI(IN2)
  • Output voltage
  • Continuous output current
  • Output capacitance

8.2.2.2 Power-Supply Considerations

TI recommends a 0.22-µF ceramic bypass capacitor between IN and GND, close to the device. The output capacitor should be chosen based on the size of the load during the transition of the switch. TI recommends a 220-µF capacitor for 100-mA loads. Typical output capacitors (xx µF, shown in Figure 15) required for a given load can be determined from Figure 7, which shows the output voltage droop when output is switched from IN2 to IN1. The output voltage droop is insignificant when output is switched from IN1 to IN2. Additionally, bypassing the output with a 1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.

8.2.2.3 Switch Transition

The N-channel MOSFET on IN1 uses a charge pump to create the gate-drive voltage, which gives the IN1 switch a rise time of approximately 0.4 ms. The P-channel MOSFET on IN2 has a simpler drive circuit that allows a rise time of approximately 4 µs. Because the device has two switches and a single enable pin, these rise times are seen as transition times, from IN1 to IN2, or IN2 to IN1, by the output. The controlled transition times help limit the surge currents seen by the power supply during switching.

8.2.2.4 Thermal Protection

Thermal protection provided on the IN1 switch prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The increased dissipation causes the junction temperature to rise to dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts it off at approximately 145°C (TJ). The switch remains off until the junction temperature has dropped approximately 10°C. The switch continues to cycle in this manner until the load fault or input power is removed.

8.2.2.5 Undervoltage Lockout

An undervoltage lockout function is provided to ensure that the power switch is in the off state at power-up. Whenever the input voltage falls below approximately 2 V, the power switch quickly turns off. This function facilitates the design of hot-insertion systems that may not have the capability to turn off the power switch before input power is removed. Upon reinsertion, the power switch is turned on with a controlled rise time to reduce EMI and voltage overshoots.

8.2.2.6 Power Dissipation and Junction Temperature

The low on-resistance on the N-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is a good design practice to check power dissipation and junction temperature. First, find ron at the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read ron from Figure 13 or Figure 14. Next calculate the power dissipation using:

Equation 1. PD = ron × I2

Finally, calculate the junction temperature:

Equation 2. TJ = PD × RθJA + TA

where

  • TA = Ambient temperature
  • RθJA = Thermal resistance

Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally sufficient to obtain a reasonable answer.

8.2.2.7 ESD Protection

All TPS2105 pins incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model, 750-V CDM, and 200-V machine-model discharge as defined in MIL-STD-883C.

8.2.3 Application Curves

C013_SLVSCH2.png
VI(IN1) = 0 V VI(IN2) = 5 V CL = 1 µF
RL = 50 Ω
Figure 16. Propagation Delay and Rise Time With
1-µF Load, IN2 Turnon
C015_SLVSCH2.png
VI(IN1) = 0 V VI(IN2) = 5 V CL = 1 µF
RL = 50 Ω
Figure 18. Propagation Delay and Fall Time With
1-µF Load, IN2 Turnoff
C014_SLVSCH2.png
VI(IN1) = 5 V VI(IN2) = 0 V CL = 1 µF
RL = 50 Ω
Figure 17. Propagation Delay and Rise Time With
1-µF Load, IN1 Turnon
C016_SLVSCH2.png
VI(IN1) = 5 V VI(IN2) = 0 V CL = 1 µF
RL = 50 Ω
Figure 19. Propagation Delay and Fall Time With
1-µF Load, IN1 Turnoff