JAJSCO4C November   2016  – September 2020 TPS22976

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics (VBIAS = 5V)
    6. 7.6  Electrical Characteristics (VBIAS = 2.5V)
    7. 7.7  Switching Characteristics (TPS22976, TPS22976N)
    8. 7.8  Switching Characteristics (TPS22976A)
    9. 7.9  Typical DC Characteristics
    10. 7.10 Typical AC Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 ON and OFF Control
      2. 9.3.2 Input Capacitor (Optional)
      3. 9.3.3 Output Capacitor (Optional)
      4. 9.3.4 Quick Output Discharge (QOD) (Not Present in TPS22976N)
      5. 9.3.5 Thermal Shutdown
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Parallel Configuration
      2. 10.1.2 Standby Power Reduction
      3. 10.1.3 Power Supply Sequencing without GPIO Input
      4. 10.1.4 Reverse Current Blocking
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
        2. 10.2.2.2 Adjustable Rise Time
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Power Dissipation
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Developmental Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Adjustable Rise Time

A capacitor to GND on the CT pins sets the slew rate for each channel. To ensure desired performance, a capacitor with a minimum voltage rating of 25 V must be used on either CT pins. An approximate formula for the relationship between CT and slew rate is shown in Equation 4, and this is valid for TPS22976 and TPS22976N. The TPS22976A has a faster rise time and is represented by Equation 5.

Equation 4 and Equation 5 account for 10% to 90% measurement on VOUT and do not apply for CT < 100 pF. Use Table 10-2 to determine rise times for when CT = 0 pF.

TPS22976, TPS22976N:
Equation 4. SR = 0.42 × CT + 66
TPS22976A:
Equation 5. SR = 0.0606 × CT + 22

where

  • SR is the slew rate (in µs/V)
  • CT is the capacitance value on the CT pin (in pF)
  • The units for the constants 66 and 22 are in µs/V.

Rise time can be calculated by multiplying the input voltage by the slew rate. Table 10-2 shows rise time values measured on a typical device. Rise times shown below are only valid for the power-up sequence where VIN and VBIAS are already in steady state condition, and the ON pin is asserted high.

Table 10-2 Rise Time Values (TPS22976, TPS22976N)
CT (pF)RISE TIME (µs) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω(1)
5 V3.3 V1.8 V1.5 V1.2 V1.05 V0.6 V
01491127770605642
220548388236206173154103
470968673401342289256169
100017681220711608505445286
220039162678155413321097949627
47008040547731792691224019641249
10000165201115064105401443039332526
TYPICAL VALUES at 25°C, VBIAS = 5 V, 25 V X7R 10% CERAMIC CAP