JAJSGC8B October   2018  – January 2020 TPS25982

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 概要 (続き)
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Protection (UVLO and UVP)
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 9.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 9.3.3.2 Circuit Breaker
        3. 9.3.3.3 Active Current Limiting
        4. 9.3.3.4 Short-Circuit Protection
      4. 9.3.4 Overtemperature Protection (OTP)
      5. 9.3.5 Analog Load Current Monitor (IMON)
      6. 9.3.6 Power Good (PG)
      7. 9.3.7 Load Detect/Handshake (LDSTRT)
    4. 9.4 Fault Response
    5. 9.5 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
        2. 10.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 10.2.2.3 Setting the Undervoltage Lockout Set Point
        4. 10.2.2.4 Choosing the Current Monitoring Resistor: RIMON
        5. 10.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 10.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 10.2.2.6 Setting the Load Handshake (LDSTRT) Delay
        7. 10.2.2.7 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        8. 10.2.2.8 Setting the Auto-Retry Delay and Number of Retries
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Optical Module Power Rail Path Protection
        1. 10.3.1.1 Design Requirements
        2. 10.3.1.2 Device Selection
        3. 10.3.1.3 External Component Settings
        4. 10.3.1.4 Voltage Drop
        5. 10.3.1.5 Application Curves
      2. 10.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
        1. 13.1.1.1 関連リンク
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.7 Load Detect/Handshake (LDSTRT)

The LDSTRT pin provides a mechanism for the downstream load circuit to indicate to the TPS25982 that the load is present and has powered up successfully. This allows the system to have additional control over the conditions in which power is presented to the load and disconnect the power when the load is not present or unable to provide a valid handshake signal after an expected boot-up time.

Once the TPS25982 completes the startup sequence and the output reaches the full voltage, it asserts the PG signal. At the same time, it also starts charging the capacitor on the LDSTRT pin (CLDSTRT) with an internal current source (ILDSTRT). If the LDSTRT pin voltage rises above VLDSTRT before the load circuit pulls it low, the TPS25982 detects the condition as a LDSTRT fault and turns off the FET to power down the load. The time to trigger the LDSTRT fault can be calculated from the following equation:

Equation 9. TPS25982 Equation-tLDSTRT.gif

During normal operation, if at any time the load circuit releases the active pull-down on the LDSTRT pin, the capacitor CLDSTRT would start charging up again and eventually trigger a shutdown due to LDSTRT fault once the capacitor charges up to VLDSTRT.

Once the TPS25982 turns off due to LDSTRT fault, it can be turned ON again in 3 ways:

  • LDSTRT pin is driven low
  • Input supply voltage is driven low (< VUVP(F)) and then driven high (> VUVP(R))
  • EN/UVLO voltage is driven low (< VSD) and then driven high (> VUVLO(R))

Tie the LDSTRT pin to ground if this functionality is not needed.

TPS25982 Timing-Diagram-LDSTRT-OK.gifFigure 48. Successful LDSTRT Handshake
TPS25982 Timing-Diagram-LDSTRT-failed.gifFigure 49. Unsuccessful LDSTRT Handshake

The LDSTRT pin can also be used to implement a load or module detect function wherein the output power is presented only when the load or module is plugged in. A typical use case for this function is on optical module power supply rails in Switches/Routers or similar networking end equipment. The LDSTRT pin should be tied to a corresponding pin on the module connector which gets pulled low by the module when it is plugged in. An example of such a signal is ModPrsL on QSFP-DD modules.

In this scheme, initially when the TPS25982 is powered up or enabled, the output charges up and PG is asserted. If the module is not plugged in, there is no external pull-down on the LDSTRT pin and the pin voltage starts rising due to internal pull-up . Once the LDSTRT pin voltage exceeds VLDSTRT, the TPS25982 turns off the output power. If the module is plugged in later, the LDSTRT pin is pulled low by the module and the TPS25982 turns on the output power.

TPS25982 Timing-Diagram-LDSTRT-Optical-module-insertion.gifFigure 50. Optical Module Plug-In Detection Using LDSTRT