JAJSGC8B October   2018  – January 2020 TPS25982

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 概要 (続き)
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Protection (UVLO and UVP)
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 9.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 9.3.3.2 Circuit Breaker
        3. 9.3.3.3 Active Current Limiting
        4. 9.3.3.4 Short-Circuit Protection
      4. 9.3.4 Overtemperature Protection (OTP)
      5. 9.3.5 Analog Load Current Monitor (IMON)
      6. 9.3.6 Power Good (PG)
      7. 9.3.7 Load Detect/Handshake (LDSTRT)
    4. 9.4 Fault Response
    5. 9.5 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
        2. 10.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 10.2.2.3 Setting the Undervoltage Lockout Set Point
        4. 10.2.2.4 Choosing the Current Monitoring Resistor: RIMON
        5. 10.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 10.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 10.2.2.6 Setting the Load Handshake (LDSTRT) Delay
        7. 10.2.2.7 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        8. 10.2.2.8 Setting the Auto-Retry Delay and Number of Retries
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Optical Module Power Rail Path Protection
        1. 10.3.1.1 Design Requirements
        2. 10.3.1.2 Device Selection
        3. 10.3.1.3 External Component Settings
        4. 10.3.1.4 Voltage Drop
        5. 10.3.1.5 Application Curves
      2. 10.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
        1. 13.1.1.1 関連リンク
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4 Fault Response

The following events trigger an internal fault which causes the device to shut down:

  • Overtemperature Protection
  • Circuit Breaker Operation
  • ITIMER pin Short to GND
  • ILIM pin Short to GND
Once the device shuts down due to a fault, even if the associated external fault is subsequently cleared, the fault stays latched internally and the output cannot turn on again until the latch is reset. The fault latch can be externally reset by one of the following methods:
  • Input supply voltage is driven low (< VUVP(F))
  • EN/UVLO voltage is driven low (< VSD)
The fault latch can also be reset by an internal auto-retry logic. The user can either disable the auto-retry behavior completely (latch-off behavior) or configure the device to auto-retry indefinitely or for a limited number of times before latching off. The auto-retry behavior is controlled by the connections on the RETRY_DLY and NRETRY pins.

Table 3. Pin Configurable Fault Response

EN/UVLO RETRY_DLY NRETRY DEVICE STATE
L X X Disabled
H Short to GND X No auto-retry (Latch-off)
H Open Open Auto-retry 4 times with minimum delay between retries and then latch-off
H Open Short to GND Auto-retry indefinitely with minimum delay between retries
H Capacitor to GND Capacitor to GND Auto-retry delay and count as per Equation 10 and Equation 11
H Capacitor to GND Open Auto-retry 4 times with finite delay between retries as per Equation 10 and then latch-off
H Capacitor to GND Short to GND Auto-retry indefinitely with finite delay between retries as per Equation 10

To configure the part for a finite number of auto-retries with a finite auto-retry delay, first choose the capacitor value on RETRY_DLY pin using the following equation.

Equation 10. TPS25982 Equation-RETRY_DLY.gif

Next, choose the capacitor value on the NRETRY pin using the following equation.

Equation 11. TPS25982 Equation-NRETRY.gif

The number of auto-retries is quantized to certain discrete levels as shown in Table 4 .

Table 4. NRETRY Quantization Levels

NRETRY Calculated From Equation 11 NRETRY Actual
0 < N < 4 4
4 < N < 16 16
16 < N < 64 64
64 < N < 256 256
256 < N < 1024 1024

Table 5. NRETRY and RETRY_DLY Combination Examples

Auto Retry Delay 915 ms 416 ms 91.7 ms 9.3 ms 3 ms
RETRY_DLY Capacitor 22 nF 10 nF 2.2 nF 220 pF 68 pF
No. of Auto Retries NRETRY Capacitor
4 Open
16 47 nF 22 nF 4.7 nF 1 nF 220 pF
64 0.22 μF 0.1 μF 22 nF 2.2 nF 1 nF
256 1 μF 0.47 μF 0.1 μF 10 nF 4.7 nF
1024 3.3 μF 1.5 μF 0.47 μF 33 nF 10 nF
Infinite Short to GND

A spreadsheet design tool TPS25982xx Design Calculator is also available for simplified calculations.

TPS25982 Timing-Diagram-Auto-retry.gifFigure 51. Auto-Retry After Fault

The auto-retry logic has a mechanism to reset the count to zero if two consecutive faults occur far apart in time. This ensures that the auto-retry response to any later fault is handled as a fresh sequence and not as a continuation of the previous fault. If the fault which triggered the shutdown and subsequent auto-retry cycle is cleared eventually and does not occur again for a duration equal to 7 retry delay timer periods starting from the last fault, the auto-retry logic resets the internal auto-retry count to zero.