JAJSRN4A July   2023  – October 2023 TPS25984

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. 概要 (続き)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Logic Interface
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Time Out
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Analog Load Current Monitor (IMON)
      6. 8.3.6  Mode Selection (MODE)
      7. 8.3.7  Parallel Device Synchronization (SWEN)
      8. 8.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.8.1 Current Balancing During Start-Up
      9. 8.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 8.3.10 Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
      12. 8.3.12 Power-Good Indication (PG)
      13. 8.3.13 Output Discharge
      14. 8.3.14 FET Health Monitoring
      15. 8.3.15 Single Point Failure Mitigation
        1. 8.3.15.1 IMON Pin Single Point Failure
        2. 8.3.15.2 ILIM Pin Single Point Failure
        3. 8.3.15.3 IREF Pin Single Point Failure
        4. 8.3.15.4 ITIMER Pin Single Point Failure
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
      3. 9.1.3 Multiple eFuses, Parallel Connection With PMBus
      4. 9.1.4 Digital Telemetry Using External Microcontroller
    2. 9.2 Typical Application: 12-V, 3.3-kW Power Path Protection in Data Center Servers
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ

Multiple Devices, Parallel Connection

Applications which need higher current capability can use two or more TPS25984x devices connected in parallel as shown in Figure 9-3.

GUID-20230719-SS0I-KPVC-4KT1-JRTLLVXM2SPH-low.svg Figure 9-2 Devices Connected in Parallel for Higher Current Capability

In this configuration, one TPS25984x device is designated as the primary device and controls the other TPS25984x devices in the chain which are designated as secondary devices. This configuration is achieved by connecting the primary device as follows:

  1. VDD is connected to IN through an R-C filter.

  2. MODE pin is left OPEN.

  3. ITIMER is connected through capacitor to GND.

  4. DVDT is connected through capacitor to GND.

  5. IREF is connected through resistor to GND.

  6. IMON is connected through resistor to GND.

  7. ILIM is connected through resistor to GND.

  8. SWEN is pulled up to a 3.3-V to 5-V standby rail. This rail must be powered up independent of the eFuse.

The secondary devices must be connected in the following manner:

  1. VDD is connected to IN through a R-C filter.

  2. MODE pin is connected to GND.

  3. ITIMER pin is left OPEN.

  4. ILIM is connected through resistor to GND.

The following pins of all devices must be connected together:

  1. IN

  2. OUT

  3. EN/UVLO

  4. DVDT

  5. SWEN

  6. PG

  7. IMON

  8. IREF

Note:

The PG pin must be pulled up to an appropriate supply voltage as per the Recommended Operating Conditions table.

In this configuration, all the devices are powered up and enabled simultaneously.

Power up: After power up or enable, all devices initially hold their SWEN low till the internal blocks are biased and initialized correctly. After that, each device releases its own SWEN. After all devices have released their SWEN, the combined SWEN goes high and the devices are ready to turn on their respective FETs at the same time.

Inrush: During inrush, because the DVDT pins are tied together to a single DVDT capacitor all the devices turn on the output with the same slew rate (SR). Choose the common DVDT capacitor (CDVDT) as per the following Equation 17 and Equation 18.

Equation 17. S R V / m s = I I N R U S H A C L O A D m F
Equation 18. C D V D T p F = 42000 S R V / m s

In this condition, the internal balancing circuit ensures that the load current is shared among all devices during start-up. This action prevents a situation where some devices turn on faster than others and experience more thermal stress as compared to other devices. This can potentially result in premature or partial shutdown of the parallel chain, or even SOA damage to the devices. The current balancing scheme ensures the inrush capability of the chain scales according to the number of devices connected in parallel, thereby ensuring successful start-up with larger output capacitances or higher loading during start-up.

All devices hold their respective PG signals low during start-up. After the output ramps up fully and reaches steady-state, each device releases its own PG pulldown. Because the DVDT pins of all devices are tied together, the internal gate high detection of all devices is synchronized. There can be some threshold or timing mismatches between devices leading to PG assertion in a staggered manner. However, because the PG pins of all devices are tied together, the combined PG signal becomes high only after all devices have released their PG pulldown. This signals the downstream load that it is okay to draw power.

Steady-state: During steady-state, all devices share current equally using the active current sharing mechanism which actively regulates the respective device RDSON to evenly distribute current across all the devices in the parallel chain.

Overcurrent during steady-state: The circuit-breaker threshold for the parallel chain is based on the total system current rather than the current flowing through individual devices. This is done by connecting the IMON pins of all the devices together. Similarly, the IREF pins of all devices are tied together and connected to a single RIREF (or an external VIREF source) to generate a common reference for the overcurrent protection block in all the devices. This action helps minimize the contribution of IIREF variation and RIREF tolerance to the overall mismatch in overcurrent threshold between devices. In this case, choose the combined RIMON as per the following Equation 19:

Equation 19. R I M O N = I I R E F × R I R E F G I M O N × I O C P T O T A L

The RILIM value for each individual eFuse must be selected based on the following Equation 20.

Equation 20. R I L I M = 1.1 × N × R I M O N 3

Where N = number of devices in parallel chain.

Other variations:

The IREF pin can be driven from an external voltage reference (VIREF).

Equation 21. R I M O N = V I R E F G I M O N × I O C P T O T A L

During an overcurrent event, the overcurrent detection of all the devices is triggered simultaneously. This in turn triggers the overcurrent blanking timer (ITIMER) on each device. However, only the primary device uses the ITIMER expiry event as a trigger to pull the SWEN low for all the devices, thereby initiating the circuit-breaker action for the whole chain. This mechanism ensures that mismatches in the current distribution, overcurrent thresholds and ITIMER intervals among the devices do not degrade the accuracy of the circuit-breaker threshold of the complete parallel chain or the overcurrent blanking interval.

However, the secondary devices also start their backup overcurrent timer and can trigger the shutdown of the whole chain if the primary device fails to do so within a certain interval.

Severe overcurrent (short-circuit): If there is a severe fault at the output (for example, output shorted to ground with a low impedance path) during steady-state operation, the current builds up rapidly to a high value and triggers the fast-trip response in each device. The devices use two thresholds for fast-trip protection – a user-adjustable threshold (ISFT = 2 × IOCP in steady-state or ISFT = 2 × ILIM during inrush) as well as a fixed threshold (IFFT only during steady-state). After the fast-trip, the devices enter into a latch-off fault condition till the device is power cycled or re-enabled or the auto-retry timer expires (only for auto-retry variants).