JAJSOU6 October 2023 TPS2HCS10-Q1
ADVANCE INFORMATION
Table 8-5 lists the memory-mapped registers for the TPS2HC10S registers. All register offset addresses not listed in Table 8-5 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 1h | CRC_CONFIG | Configure CRC | Go |
| 2h | SLEEP | Sets to go into SLEEP sate from ACTIVE or STANDBY state | Go |
| 3h | LPM | Sets to go in or out of Low power mode (LPM STATE) | Go |
| 4h | CH_FLT_TYPE_FAULT_GLOBAL_TYPE | Faults for any channel and global faults | Go |
| 5h | FAULT_MASK | Mask the reporting of the faults on the fault pin | Go |
| 6h | ABIST_RESULT | ABIST Diagniostic result | Go |
| 7h | SW_STATE | Turn on/off OUTx | Go |
| 8h | DEVICE_SAF | Device BIST, LIMPHOME, and locking set by SPI | Go |
| 9h | DEV_CONFIG | Device Configureable settings register | Go |
| Ah | ADC_CONFIG | ADC configuration - disable ADC conversions or ADC entirely | Go |
| Bh | ADC_RESULT_VBB | ADC conversion result VBB | Go |
| Dh | FLT_STAT_CH1 | Status of the channels and channel faults | Go |
| Eh | PWM_CH1 | Set all PWM configurations for channel 1 | Go |
| Fh | ILIM_CONFIG_CH1 | Set all current limit configuration for channel 1 | Go |
| 10h | DIAG_CONFIG_CH1 | Configuration register for channel 1 | Go |
| 11h | ADC_RESULT_CH1_I | ADC conversion result load current sense CH1 | Go |
| 12h | ADC_RESULT_CH1_T | ADC conversion result TJ sense CH1 | Go |
| 13h | ADC_RESULT_CH1_V | ADC conversion result VOUT sense CH1 | Go |
| 14h | I2T_CONFIG_CH1 | Set all I2T configuration bits | Go |
| 15h | FLT_STAT_CH2 | Status of the channels and channel faults | Go |
| 16h | PWM_CH2 | Set all PWM configurations for channel 2 | Go |
| 17h | ILIM_CONFIG_CH2 | Set all current limit configuration for channel 2 | Go |
| 18h | DIAG_CONFIG_CH2 | Configuration register for channel 2 | Go |
| 19h | ADC_RESULT_CH2_I | ADC conversion result load current sense CH2 | Go |
| 1Ah | ADC_RESULT_CH2_T | ADC conversion result TJ sense CH2 | Go |
| 1Bh | ADC_RESULT_CH2_V | ADC conversion result VOUT sense CH2 | Go |
| 1Ch | I2T_CONFIG_CH2 | Set all I2T configuration bits | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-6 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C | Write 1 to clear |
| WC | W C | Write to Clear |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
CRC_CONFIG is shown in Table 8-7.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | CRC_EN | R/W | 0h | Set this bit to 1 to enable CRC check of SPI command frame.
0h = No CRC check of SPI command frame 1h = CRC check of SPI command frame enabled |
SLEEP is shown in Table 8-8.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | SLEEP | R/W | 0h | Setting this bit to 1 puts the device into SLEEP mode where everything shuts off |
LPM is shown in Table 8-9.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-9 | RESERVED | R | 0h | Reserved |
| 8-7 | RESERVED | R | 0h | Reserved |
| 6-5 | RESERVED | R | 0h | Reserved |
| 4-3 | LPM_EXIT_CURR_CH2 | R/W | 0h | Set the threshold for exit from LPM mode due to load current increase - CH2.
0h = 600 mA 1h = 800 mA 2h = 200 mA 3h = 400 mA |
| 2-1 | LPM_EXIT_CURR_CH1 | R/W | 0h | Set the threshold for exit from LPM mode due to load current increase - CH1.
0h = 600 mA 1h = 800 mA 2h = 200 mA 3h = 400 mA |
| 0 | LPM | R/W | 0h | Setting this bit to 1 puts the device into LPM mode with the channels enabled as per the device |
CH_FLT_TYPE_FAULT_GLOBAL_TYPE is shown in Table 8-10.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | I2T_FLT | R | 0h | The bit is set if there is a I2T fault due to ovecurrent in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists. |
| 14 | LPM_FLT | R | 0h | The bit is set if there is a fault during low power mode and the chip comes back to the active state. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists |
| 13 | CHAN_TSD | R | 0h | The bit is set if there is a thermal shutdown fault due to thermal overload in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists.
0h = no thermal shutdown fault in any of the channels 1h = thermal shutdown fault in one of the channels |
| 12 | ILIMIT_FLT | R | 0h | The bit is set if there is a FET turn-off fault due to ovecurrent in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists.
0h = no overcurrent fault in any of the channels 1h = overcurrent fault in one of the channels |
| 11 | SHRT_VBB_FLT | R | 0h | The bit is set if there is a short to VBB supply in the off-state fault in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists
0h = no off-state short to VBB fault in any of the channels 1h = off-state short to VBB fault in one of the channels |
| 10 | OL_FLT | R | 0h | The bit is set if either there is a wire break in the on or off-state fault in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists
0h = no on or off-state open laod detection fault in any of the channels 1h = on or off-state open load detection fault in one of the channels |
| 9 | SUPPLY_FLT | R | 1h | The bit is set if either the VDD_UVLO or VBB_UV are faults occur. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition no longer exists.
0h = no UV fault in VDD, VINT or VBB 1h = UV fault in VDD, VINT or VBB |
| 8 | GLOBAL_ERR_WRN | R | 1h | The bit is set if there is a global fault reported in the FLT_GLOBAL_TYPE register (Bits [7:0] : SPI error, watchdog error, VBB_UV, VBB_UV_WRN, VDD_UVLO, POR fault or LIMPHOME_STAT bit is set. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_GLOBAL_TYPE register is read and the fault condition no longer exists.
0h = no global fault 1h = One of the following errors have occurred: SPI error, watchdog error, VBB_UV, VBB_UV_WRN, VDD_UVLO, POR fault or LIMPHOME_STAT bit is set |
| 7 | LIMPHOME_STAT | W1C | 0h | This bit is set high if the device is currently in the limp home mode. |
| 6 | POR | R/WC | 1h | The bit is indicative of whether a power on reset has occurred.
0h = There is no power-on reset anytime after the last register read The register bit is cleared on read, so if read again and the bit is 0, means that no power-on reset has occurred since the read. 1h = A power-on reset has occurred since the last register read. |
| 5 | RESERVED | R | 0h | Reserved |
| 4 | SPI_ERR | R/WC | 0h | The bit is set if there is an SPI communication error either from format, clock or CRC errors.The fault bit is latched and cleared only after read and the error is removed.
0h = No SPI communication error fault 1h = SPI communication error either from format, clock or CRC has occurred |
| 3 | WD_ERR | R/WC | 0h | The bit is set if the watchdog timer is enabled and there has not been an acceptable SPI command in the watchdog timeout window. The fault bit is latched and cleared only after read and the error is removed.
0h = No SPI interface watchdog error 1h = SPI watchdog timeout error has occurred |
| 2 | VDD_UVLO | R/WC | 1h | The bit is set if VDD supply is below the UVLO threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UVLO condition is removed
0h = No VDD UVLO fault 1h = VDD UVLO fault |
| 1 | VBB_UV_WRN | R/WC | 1h | The bit is set if VBB supply is below the UV warning (UV_WRN) threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UV condition is removed
0h = No VBB UV_WRN fault 1h = VBB UV_WRN fault |
| 0 | VBB_UVLO | R/WC | 1h | The bit is set if VBB supply is below the UV threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UV condition is removed
0h = No VBB UV fault 1h = VBB UV fault |
FAULT_MASK is shown in Table 8-11.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6 | MASK_ILIMIT | R/W | 0h | The bit is set to mask the signaling overcurrent protection fault on the FLT pin
0h = Fault is signaled on the FLT pin on overcurrent FET turn-off occuring 1h = Overcurrent protection fault is not signaled (masked from) on the FLT pin |
| 5 | MASK_SHRT_VBB | R/W | 0h | The bit is set to mask the signaling off-state Short to VBB fault on the FLT pin
0h = Short to VBB Fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = Short to VBB fault is not signaled (masked from) on the FLT pin |
| 4 | MASK_OL_OFF | R/W | 0h | The bit is set to mask the signaling off-state open load fault on the FLT pin
0h = Off-state wire-break fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = Off-state wire-break fault is not signaled (masked from) on the FLT pin |
| 3 | MASK_OL_ON | R/W | 0h | The bit is set to mask the signaling on-state open load fault on the FLT pin
0h = On-state wire-break fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = On-state wire-break fault is not signaled (masked from) on the FLT pin |
| 2 | MASK_SPI_ERR | R/W | 0h | The bit is set to mask the SPI error (SPI_ERR) signaling in the FLT pin output and FAULT_TYPE_STAT register
0h = SPI error is signaled in FAULT_TYPE_STAT register and FLT pin 1h = FAULT_TYPE_STAT register and FLT pin not impacted by SPI error |
| 1 | MASK_WD_ERR | R/W | 0h | The bit is set to mask the SPI watchdog error (WD_ERR) signaling in the FLT pin output and FAULT_TYPE_STAT register
0h = SPI watchdog error is signaled in FAULT_TYPE_STAT register and FLT pin 1h = FAULT_TYPE_STAT register and FLT pin not impacted by SPI watchdog error |
| 0 | MASK_VBB_UVLO | R/W | 0h | The bit is set to mask the supply voltage VBB UVLO fault signaling on the FLT pin output.
0h = VBB UV fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = VBB UV fault is not signaled (masked from) on the FLT pin |
ABIST_RESULT is shown in Table 8-12.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | ADC_GOOD | R | 0h | This says whether or not the ABIST for the ADC passed (not implemented in the present release)
0h = ABIST for ADC Passed 1h = ABIST for ADC Failed |
| 2 | ISNS_GOOD | R | 0h | This says whether or not the ABIST for the ISNS passed (not implemented in the present release)
0h = ABIST for ISNSPassed 1h = ABIST for ISNS Failed |
| 1 | VBB_UVP_GOOD | R | 0h | This says whether or not the ABIST for the VBB passed (not implemented in the present release)
0h = ABIST for VBB Passed 1h = ABIST for VBB Failed |
| 0 | BG_GOOD | R | 0h | This says whether or not the ABIST for the Bandgap passed (not implemented in the present release)
0h = ABIST for BG Passed 1h = ABIST for BG Failed |
SW_STATE is shown in Table 8-13.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0h | Reserved |
| 1 | CH2_ON | R/W | 0h | Set this bit to 1 to turn on the FET and CH2 output ON
0h = CH2 Output set to OFF (FET is OFF). 1h = CH2 Output set to ON (FET is ON). |
| 0 | CH1_ON | R/W | 0h | Set this bit to 1 to turn on the FET and CH1 output ON
0h = CH1 Output set to OFF (FET is OFF). 1h = CH1 Output set to ON (FET is ON). |
DEVICE_SAF is shown in Table 8-14.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12-11 | RESERVED | R | 0h | Reserved |
| 10-9 | RESERVED | R | 0h | Reserved |
| 8-7 | CH2_LH_IN | R/W | 0h | Decides what to do with the output for LH mode. Either on, off, keep or use associated DI pin
0h = DI control output when in LHM 1h = keep output as it enter LHM 2h = output will be off during LHM 3h = output will be on during LHM |
| 6-5 | CH1_LH_IN | R/W | 0h | Decides what to do with the output for LH mode. Either on, off, keep or use associated DI pin
0h = DI control output when in LHM 1h = keep output as it enter LHM 2h = output will be off during LHM 3h = output will be on during LHM |
| 4 | ADC_ABIST_RUN | R/W | 0h | Run the ABIST diaagnostics for the ADC good signal and update the DIAG_RESULT register with the result. Not available in current silicon, but will be in the production version. Not available with in I2T loop. Reset bit back to 0 after ABIST has been run
0h = ABIST not Running 1h = ABIST for ADC Running |
| 3 | ISNS_ABIST_RUN | R/W | 0h | Run the ABIST diaagnostics for the ISNS good signal and update the DIAG_RESULT register with the result. Not available when in I2T loop. Reset bit back to 0 after ABIST has been run
0h = ABIST not Running 1h = ABIST for ISNS Running |
| 2 | RESERVED | R | 0h | Reserved |
| 1 | BG_ABIST_RUN | R/W | 0h | Run the ABIST diaagnostics for the Band Gap good signal and update the DIAG_RESULT register with the result. Reset bit back to 0 after ABIST has been run
0h = ABIST not Running 1h = ABIST for BG Running |
| 0 | ADC_EN | R/W | 0h | Setting this bit to 1, enables the ADC function
0h = ADC function disabled 1h = ADC enabled |
DEV_CONFIG is shown in Table 8-15.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6 | PWM_SHIFT_DIS | R/W | 0h | Set this bit to 1 to disable the PWM delay between channels.
0h = PWM rising edges delayed by 100 us on the first rising edge 1h = PWM delay (offset) is disabled so rising edges are aligned |
| 5 | RESERVED | R | 0h | Reserved |
| 4 | PARALLEL_12 | R/W | 0h | Set this bit to 1 to signal that channels 1 and 2 (CH1 and CH2) are paralleled. Write to this bit is valid only when all SW_STATE Channel enable bits are 0 and not rewritten to 1 in the same frame.
0h = CH1 and CH2 are not paralleled together 1h = CH1 and CH2 are paralleled together |
| 3 | WD_EN | R/W | 0h | The bit is set to enable the watchdog function. The watchdog is triggered if there is not a valid SPI command in the watchdog timeout window
0h = Watchdog is disabled 1h = Watchdog function is enabled |
| 2-1 | WD_TO | R/W | 0h | Sets the timeout period for the SPI watchdog monitor. The watchdog timeout is triggered if there is not a valid SPI command in the watchdog timeout window
0h = Watchdog timeout 400 us 1h = Watchdog timeout is 400 ms 2h = Watchdog timeout is 800 ms 3h = Watchdog timeout is 1200 ms |
| 0 | FLT_LTCH_DIS | R/W | 0h | Set this bit to 1 to not latch the fault bits in the register and cleared on read.
0h = Fault bits in FAULT_TYPE_STAT register latched and cleared only on read 1h = Fault bits in FAULT_TYPE_STAT register not latched, cleared when the fault disappears |
ADC_CONFIG is shown in Table 8-16.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-5 | RESERVED | R | 0h | Reserved |
| 4 | ADC_VSNS_DIS | R/W | 1h | Set this bit to 1 to disable VOUT sense functionality, exclude VOUT conversion in the ADC conversion sequence.
0h = VOUTSNS ADC functionality enabled, include VOUT_SNS ADC conversion in the sequence 1h = VOUTSNS ADC functionality is disabled |
| 3 | ADC_TSNS_DIS | R/W | 1h | Set this bit to 1 to disable TEMP sense functionality, exclude TSNS conversion in the ADC conversion sequence.
0h = TSNS ADC functionality enabled, include TSNS ADC conversion in the sequence 1h = TSNS ADC functionality is disabled |
| 2 | ADC_ISNS_DIS | R/W | 0h | Set this bit to 1 to disable ISNS functionality, exclude ISNS conversion in the ADC conversion sequence.
0h = ISNS ADC functionality enabled, include ISNS ADC conversion in the sequence 1h = ISNS ADC functionality is disabled |
| 1 | ADC_VBB_DIS | R/W | 1h | Set this bit to 1 to disable VBB_SNS functionality, exclude supply voltage V_VBB conversion in the ADC conversion sequence.
0h = VBB_SNS ADC functionality is enabled, Include supply voltage V_VBB ADC conversion in the sequence 1h = VBB_SNS ADC functionality is disabled |
| 0 | RESERVED | R | 0h | Reserved |
ADC_RESULT_VBB is shown in Table 8-17.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | VBB_RDY | R | 0h | Making sure the ADC conversion is new from the last time this was read
0h = VBB ADC Value not updated 1h = New VBB ADC Value Ready |
| 9-0 | ADC_RESULT_VBB | R | 0h | ADC result (10-bits) from the conversion of the VBB voltage |
FLT_STAT_CH1 is shown in Table 8-18.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | LATCH_STAT_CH1 | R | 0h | The bit is high if the channel has been latched off after a fault that shut down the channel. Clears when the channel is toggled back on
0h = CH1 is not latched off 1h = CH1 is currently latched off |
| 10 | FLT_CH1 | R | 0h | The bit is set if any type of real time fault (reverse current, thermal shutdown, open load (on/off-state) or short to supply) occurs in CH1
0h = No fault in CH1 1h = One or more fault has occurred in CH1 |
| 9 | SW_STATE_STAT_CH1 | R | 0h | Current state of the channel no matter which mode the device is in as long as SPI is readable
0h = CH1 is OFF 1h = CH1 is ON |
| 8 | RESERVED | R | 0h | Reserved |
| 7 | I2T_FLT_CH1 | R | 0h | The bit is set if there is a fault from I2T setting (overcurrent). Only can go high if I2T_EN is high and an associated fault occurs on that channel. Cleared when FLT_STAT_CH1 register is read and fault condition does not exist anymore
0h = no I2T fault or I2T is not enabled 1h = I2T fault has occurred on CH1 |
| 6 | LPM_WAKE_CH1 | R | 0h | This bit is set if this channel was the reason the device came out of LPM regardless of why
0h = The device was not in LPM or this channel was not the one that cause the device to come out of LPM 1h = This channel was the reason the device came out of LPM |
| 5 | THERMAL_SD_CH1 | R | 0h | The bit is set if the thermal shutdown has occurred at any time in CH1. The fault is latched and cleared when the FLT_STAT_CH1 register is read and channel temperature has fallen below the thermal shutdown reset threshold.
0h = No thermal shutdown fault in CH1 1h = Thermal shutdown has occurred in CH1 |
| 4 | ILIMIT_CH1 | R | 0h | The bit is set if FET turn-off due to overcurrent has occurred at any time in CH1. The fault is latched and cleared when the FLT_STAT_CH1 register is read and fault condition does not exist anymore. Disabled if I2T mode is enabled
0h = No overcurrent protection fault in CH1 1h = FET turn-off due to overcurrent fault has occurred in CH1 |
| 3 | SHRT_VBB_CH1 | R | 0h | The bit is set if short to VBB has occurred at any time in CH1. The fault is latched and cleared when the FLT_STAT_CH1 register is read and fault condition does not exist anymore. OL_SHRTVBB_DIFF_CH1 must have been enabled previously
0h = No Short to VBB fault in CH1 or short to VBB in OFF state not enabled 1h = Short to VBB Fault |
| 2 | OL_OFF_CH1 | R | 0h | The bit is set if the open load off state threshold been triggered. Only valid if OL_OFF_EN_CH1 is active. Device is pulled up with the threshold set by OL_PULLUP_STR
0h = No off state open load fault in CH1 or OL detection in OFF state not enabled 1h = Off State Open Load Fault |
| 1 | OL_ON_CH1 | R | 0h | Has the open load on state threshold been triggered? Only valid if OL_ON_EN_CH1 is active. Device is in high resistance mode
0h = No on state open load fault in CH1 or OL detection in OFF state not enabled 1h = On State Open Load Fault |
| 0 | THERMAL_WRN_CH1 | R | 0h | The bit is set if FET temperature is above the overtemperature warning threshold in CH1. The bit is cleared when over-temperature earning condition does not exist anymore.
0h = FET temperatire below over-temperature warning threshold in CH1 1h = FET temperatire above over-temperature warning threshold in CH1 |
PWM_CH1 is shown in Table 8-19.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-9 | PWM_FREQ_CH1 | R/W | 0h | Set the PWM frequency
0h = 0.8 Hz 1h = 3.4 Hz 2h = 13.8 Hz 3h = 111 Hz 4h = 221 Hz 5h = 443 Hz 6h = 885 Hz 7h = 1770 Hz |
| 8-1 | PWM_DTY_CH1 | R/W | 0h | 8 bit to set duty cycle for PWM operation of CH1. Each bit ~0.39% duty cycle, linearly up to 100% dutycycle. |
| 0 | PWM_EN_CH1 | R/W | 0h | Enable PWMing of the output if on cycle of PWM is >200us. If not return error in FLT_STAT_CH1 register. PWM mode cannot be enabled unless CAP_CHRGx [1:0] = 00
0h = Output follows SW_STATE behavior (ON/OFF) 1h = Output is PWMing according to duty cycle and frequency set if SW_STATE CH1 is ON |
ILIM_CONFIG_CH1 is shown in Table 8-20.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | OCP_INRUSH_CH1 | R/W | 0h | When CAP_CHRG=11, sets the overcurrent turn-off threshold during inrush phase and thus the peak current of the current pulse.
0h = Sets overcurrent turn-off and peak current to 47.5A 1h = Sets overcurrent turn-off and peak current to 55 A Ah = Sets overcurrent turn-off and peak current to 62.5 A Bh = Sets overcurrent turn-off and peak current to 70 A |
| 13-12 | CAP_CHRG_CH1 | R/W | 0h | Puts the part into the capacitive load driving mode. Turns on the INRUSH_LIMIT_CH1 bits to set the overcurrent protection or cap charging levels within the INRUSH_DURATION period and during that time there is no PWM or I2T
0h = No cap charging mode (immediate shutdown only) 1h = Cap charging mode dV/dt 2h = Cap charging mode current limit regulation mode. 3h = Cap charging mode - current pulse method |
| 11 | I2T_EN_CH1 | R/W | 0h | Enables the I2T functionality for Channel 1. I2T can be enabled before the channel is enabled or charges up, but the I2T calculation will start after the cap charge period ends If the cap charging mode is enabled (CAP_CHRG_CH1 [1:0] ne 00) .
0h = I2T functionality not enabled 1h = I2T functionality is enabled |
| 10-8 | INRUSH_DURATION_CH1 | R/W | 0h | Sets the delay period during with inrush current limit level applies.
0h = 0 1h = 2 2h = 4 3h = 6 4h = 10 5h = 20 6h = 50 7h = 100 ms |
| 7-4 | INRUSH_LIMIT_CH1_OR_CAP_CHRG_DVDT | R/W | 8h | Overcurrent protection thresholds if CAP_CHRG_CH1 = 00. Becomes cap charging mode control bits when in cap charging mode. This means instead of having an overcurrent protection threshold setting for an inrush period, the bits are used to set the cap charging control bits setting either the dV/dt rate (CAP_CHRG_CH1 = 01), current limit (regulation) level (CAP_CHRG_CH1 = 10) or pulsed current mode parameters. (CAP_CHRG_CH1 = 11).
When CAP_CHRG_CH1 = 00, then the same table as ILIMIT_SET_CH1 applies for overcurrent protection threshold during the INRUSH_DURATION.
When CAP_CHRG_CH1 = 10, then the current limit threshold is below table with the value divided by 5.
When CAP_CHRG_CH1 = 01, 4-bits will be used to set the dV/dt or voltage ramp rate per the table below. Only the specified bit settings are supported.
3h = 2.22 V/ms 5h = 1.0 V/ms 6h = 1.33 V/ms 7h = 1.66 V/ms 9h = 0.67 V/ms Ah = 0.89 V/ms Bh = 1.1 V/ms Ch = 0.33 V/ms Dh = 0.50 V/ms |
| 3-0 | ILIMIT_SET_CH1 | R/W | 8h | Setting the overcurrent protection threshold after the INRUSH_DURATION period.
0h = 10 A 1h = 12.5 A 2h = 15 A 3h = 17.5 A 4h = 20 A 5h = 22.5 A 6h = 25 A 7h = 32.5 A 8h = 40 A 9h = 47.5 A Ah = 55 A Bh = 62.5 A Ch = 70 A Other settings are not supported. |
DIAG_CONFIG_CH1 is shown in Table 8-21.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | VSNS_DIS_CH1 | R/W | 1h | Set this bit to 1 to disable the VSNS ADC functionality for this channel
0h = VSNS ADC functionality enabled 1h = VSNS ADC functionality is disabled |
| 14 | TSNS_DIS_CH1 | R/W | 1h | Set this bit to 1 to disable the ADC TSNS functionality for this channel
0h = TSNS ADC functionality enabled 1h = TSNS ADC functionality is disabled |
| 13 | ISNS_DIS_CH1 | R/W | 0h | Set this bit to 1 to disable ISNS ADC functionality for this channel
0h = ISNS ADC functionality enabled 1h = ISNS ADC functionality is disabled |
| 12-11 | OL_ON_THLD_CH1 | R/W | 0h | Sets the open load detection threshold in the on state. 2 bits to set the open load detection threshold, not implemented in current silicon revision
0h = TBD 1h = TBD 2h = TBD 3h = TBD |
| 10 | ISNS_SCALE_CH1 | R/W | 0h | Turns on 8x scaling of voltage input to the ADC to improve the current sense resolution
0h = ADC input voltage scale equals 1 1h = ADC input voltage scale equals 8 |
| 9 | OL_ON_EN_CH1 | R/W | 0h | Turns on a more accurate open load detection in the on state with KSNS ratio scaled to lower value. This will set the FET into high Rdson mode therefore this cannot be enabled if there is an existing fault on the channel or the current is too high
0h = KSNS ratio and FET Rdson unchanged 1h = Enable Open Load Detection with a lower KSNS ratio and higher Rdson |
| 8-7 | OL_SVBB_BLANK_CH1 | R/W | 0h | Sets the blanking time for open load (ON-state and OFF-state) and the short_to_VBB faults before the fault is registered.
0h = Blanking time is 0.4 ms 1h = Blanking time is 1.0 ms 2h = Blanking time is 2.0 ms 3h = Blanking time is 4.0 ms |
| 6-5 | OL_PU_STR_CH1 | R/W | 0h | Sets the pullup current value (at the OUTx pins) by the off-state open load detection circuit.
0h = I_pu is 32 uA 1h = I_pu is 64 uA 2h = I_pu is 128 uA 3h = I_pu is 256 uA |
| 4 | OL_OFF_EN_CH1 | R/W | 0h | Turns on the pull up to see if there is an open load in the off state. Cannot bet set high if channel is on or fault exists |
| 3 | SVBB_EN_CH1 | R/W | 0h | Turns on the pull down to see if there is a short to VBB in the off state. Cannot bet set high if channel is on or fault exists |
| 2 | LATCH_CH1 | R/W | 0h | If fault occurs that channel shuts down, this bit sets if the channel auto retries or latches off
0h = Auto retry after tRETRY and Thys 1h = latch off until SW_STATE register is written to again |
| 1-0 | SLRT_CH1 | R/W | 2h | Slew Rate set for ouput of CH1. 4 different slew rate values for adjustable slew rate per electrical characteristics table |
ADC_RESULT_CH1_I is shown in Table 8-22.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | ISNS_RDY_CH1 | R | 0h | Making sure the ADC conversion is new from the last time this was read |
| 9-0 | ADC_RESULT_CH1_I | R | 0h | ADC result (10-bits) from the conversion of the current in CH1 |
ADC_RESULT_CH1_T is shown in Table 8-23.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | TSNS_RDY_CH1 | R | 0h | Making sure the ADC conversion is new from the last time this was read |
| 9-0 | ADC_RESULT_CH1_T | R | 0h | ADC result (10-bits) from the conversion of the temperature in CH1 |
ADC_RESULT_CH1_V is shown in Table 8-24.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | VSNS_RDY_CH1 | R | 0h | Making sure the ADC conversion is new from the last time this was read |
| 9-0 | ADC_RESULT_CH1_V | R | 0h | ADC result (10-bits) from the conversion of the output voltage in CH1 |
I2T_CONFIG_CH1 is shown in Table 8-25.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | TCLDN_CH1 | R/W | 0h | 2bits to Set cool down time for I2T functionality for Channel 1 (time to retry after I2T shutdown.
0h = Latch mode (or no retry) 1h = 0.8 s 2h = 2.0 s 3h = 4.0 s |
| 13-11 | RESERVED | R | 0h | Reserved |
| 10-9 | SWCL_DLY_TMR_CH1 | R/W | 0h | 2-bits to set delayed turn-off timer for Channel 1. Sets the time after which the channel shuts down when the current exceeds ISWCL.
0h = 0.2 ms 1h = 0.4 ms 2h = 1.0 ms 3h = 2.0 ms |
| 8-7 | ISWCL_CH1 | R/W | 0h | 2bits to set delayed turn-off current threshold value for I2T functionality for Channel 1. The threshold should be set below the maximum current sensed with the sense resistor chosen. The current threshold assumes a sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs
0h = 19.55 1h = 17.6 2h = 16.05 3h = 13.3 |
| 6-3 | I2T_TRIP_CH1 | R/W | 0h | 4bits to Set Trip value for I2T functionality for Channel 1. Assumes sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs and the threshold changes by the square of the current.
0h = 8.8 A2s 1h = 13.1 A2s 2h = 26.3 A2s 3h = 39.4 A2s 4h = 52.5 A2s 5h = 65.6 A2s 6h = 78.8 A2s 7h = 91.9 A2s 8h = 109.4 A2s 9h = 126.9 A2s Ah = 144.4 A2s Bh = 166.3 A2s Ch = 192.5 A2s Dh = 218.8 A2s Eh = 262.5 A2s Fh = 350 A2s |
| 2-0 | NOM_CUR_CH1 | R/W | 0h | 3 bits to set the nomial current value of Channel 1. Assumes sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs
0h = 4.0 A 1h = 5.0 A 2h = 5.7 A 3h = 6.5 A 4h = 7.5 A 5h = 9.0 A 6h = 12.0 A 7h = 15.0 A |
FLT_STAT_CH2 is shown in Table 8-26.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | LATCH_STAT_CH2 | R | 0h | The bit is high if the channel has been latched off after a fault that shut down the channel. Clears when the channel is toggled back on
0h = CH2 is not latched off 1h = CH2 is currently latched off |
| 10 | FLT_CH2 | R | 0h | The bit is set if any type of real time fault (reverse current, thermal shutdown, open load (on/off-state) or short to supply) occurs in CH2
0h = No fault in CH2 1h = One or more fault has occurred in CH2 |
| 9 | SW_STATE_STAT_CH2 | R | 0h | Current state of the channel no matter which mode the device is in as long as SPI is readable
0h = CH2 is OFF 1h = CH2 is ON |
| 8 | RESERVED | R | 0h | Reserved |
| 7 | I2T_FLT_CH2 | R | 0h | The bit is set if there is a fault from I2T setting (overcurrent). Only can go high if I2T_EN is high and an associated fault occurs on that channel. Cleared when FLT_STAT_CH2 register is read and fault condition does not exist anymore
0h = no I2T fault or I2T is not enabled 1h = I2T fault has occurred on CH2 |
| 6 | LPM_WAKE_CH2 | R | 0h | This bit is set if this channel was the reason the device came out of LPM regardless of why
0h = The device was not in LPM or this channel was not the one that cause the device to come out of LPM 1h = This channel was the reason the device came out of LPM |
| 5 | THERMAL_SD_CH2 | R | 0h | The bit is set if the thermal shutdown has occurred at any time in CH2. The fault is latched and cleared when the FLT_STAT_CH2 register is read and channel temperature has fallen below the thermal shutdown reset threshold.
0h = No thermal shutdown fault in CH2 1h = Thermal shutdown has occurred in CH2 |
| 4 | ILIMIT_CH2 | R | 0h | The bit is set if FET turn-off due to overcurrent has occurred at any time in CH2. The fault is latched and cleared when the FLT_STAT_CH2 register is read and fault condition does not exist anymore.
0h = No overcurrent rprotection fault in CH2 1h = FET turn-off due to overcurrent fault has occurred in CH2 |
| 3 | SHRT_VBB_CH2 | R | 0h | The bit is set if short to VBB has occurred at any time in CH2. The fault is latched and cleared when the FLT_STAT_CH2 register is read and fault condition does not exist anymore. OL_SHRTVBB_DIFF_CH2 must have been enabled previously
0h = No Short to VBB fault in CH2 or short to VBB in OFF state not enabled 1h = Short to VBB Fault |
| 2 | OL_OFF_CH2 | R | 0h | Has the open load off state threshold been triggered? Only valid if OL_OFF_EN_CH2 is active. Device is pulled up with the threshold set by OL_PULLUP_STR
0h = No off state open load fault in CH2 or OL detection in OFF state not enabled 1h = Off State Open Load Fault |
| 1 | OL_ON_CH2 | R | 0h | Has the open load on state threshold been triggered? Only valid if OL_ON_EN_CH2 is active. Device is in high resistance mode
0h = No on state open load fault in CH2 or OL detection in OFF state not enabled 1h = On State Open Load Fault |
| 0 | THERMAL_WRN_CH2 | R | 0h | The bit is set if FET temperature is above the overtemperature warning threshold in CH2. The bit is cleared when over-temperature earning condition does not exist anymore.
0h = FET temperatire below over-temperature warning threshold in CH2 1h = FET temperatire above over-temperature warning threshold in CH2 |
PWM_CH2 is shown in Table 8-27.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11-9 | PWM_FREQ_CH2 | R/W | 0h | Set the PWM frequency
0h = 0.8 Hz 1h = 3.4 Hz 2h = 13.8 Hz 3h = 111 Hz 4h = 221 Hz 5h = 443 Hz 6h = 885 Hz 7h = 1770 Hz |
| 8-1 | PWM_DTY_CH2 | R/W | 0h | 8 bit to set duty cycle for PWM operation of CH2. Each bit ~0.39% duty cycle |
| 0 | PWM_EN_CH2 | R/W | 0h | Enable PWMing of the output if on cycle of PWM is >200us. If not return error in FLT_STAT_CH2 register. PWM mode cannot be enabled unless CAP_CHRGx [1:0] = 00
0h = Output follows SW_STATE behavior (ON/OFF) 1h = Output is PWMing according to duty cycle and frequency set if SW_STATE CH2 is ON |
ILIM_CONFIG_CH2 is shown in Table 8-28.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | OCP_INRUSH_CH2 | R/W | 0h | When CAP_CHRG=11, sets the overcurrent turn-off threshold during inrush phase and thus the peak current of the current pulse.
0h = Sets overcurrent turn-off and peak current to 47.5A 1h = Sets overcurrent turn-off and peak current to 55 A Ah = Sets overcurrent turn-off and peak current to 62.5 A Bh = Sets overcurrent turn-off and peak current to 70 A |
| 13-12 | CAP_CHRG_CH2 | R/W | 0h | Puts the part into the capacitive load driving mode. Turns on the INRUSH_LIMIT_CH2 bits to set the overcurrent protection or cap charging levels within the INRUSH_DURATION period and during that time there is no PWM or I2T
0h = No cap charging mode (immediate shutdown only) 1h = Cap charging mode dV/dt 2h = Cap charging mode current limit regulation mode. 3h = Cap charging mode - current pulse method |
| 11 | I2T_EN_CH2 | R/W | 0h | Enables the I2T functionality for Channel 2. I2T can be enabled before the channel is enabled or charges up, but the I2T calculation will start after the cap charge period ends If the cap charging mode is enabled (CAP_CHRG_CH2 [1:0] ne 00) . |
| 10-8 | INRUSH_DURATION_CH2 | R/W | 0h | Sets the delay period during with inrush current limit level applies. See table of delay settings in the datasheet.
0h = 0 1h = 2 2h = 4 3h = 6 4h = 10 5h = 20 6h = 50 7h = 100 ms |
| 7-4 | INRUSH_LIMIT_CH2_OR_CAP_CHRG_DVDT | R/W | 8h | Overcurrent protection thresholds if CAP_CHRG_CH1 = 00. Becomes cap charging mode control bits when in cap charging mode. This means instead of having an overcurrent protection threshold setting for an inrush period, the bits are used to set the cap charging control bits setting either the dV/dt rate (CAP_CHRG_CH1 = 01), current limit (regulation) level (CAP_CHRG_CH1 = 10) or pulsed current mode parameters. (CAP_CHRG_CH1 = 11).
When CAP_CHRG_CH1 = 00, then the same table as ILIMIT_SET_CH1 applies for overcurrent protection threshold during the INRUSH_DURATION.
When CAP_CHRG_CH1 = 10, then the current limit threshold is below table with the value divided by 5.
When CAP_CHRG_CH1 = 01, 4-bits will be used to set the dV/dt or voltage ramp rate per the table below. Only the specified bit settings are supported.
3h = 2.22 V/ms 5h = 1.0 V/ms 6h = 1.33 V/ms 7h = 1.66 V/ms 9h = 0.67 V/ms Ah = 0.89 V/ms Bh = 1.1 V/ms Ch = 0.33 V/ms Dh = 0.50 V/ms |
| 3-0 | ILIMIT_SET_CH2 | R/W | 8h | Setting the overcurrent protection threshold after the INRUSH_DURATION period.
0h = 10 A 1h = 12.5 A 2h = 15 A 3h = 17.5 A 4h = 20 A 5h = 22.5 A 6h = 25 A 7h = 32.5 A 8h = 40 A 9h = 47.5 A Ah = 55 A Bh = 62.5 A Ch = 70 A Other settings are not supported. |
DIAG_CONFIG_CH2 is shown in Table 8-29.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | VSNS_DIS_CH2 | R/W | 1h | Set this bit to 1 to disable the VSNS ADC functionality for this channel
0h = VSNS ADC functionality enabled 1h = VSNS ADC functionality is disabled |
| 14 | TSNS_DIS_CH2 | R/W | 1h | Set this bit to 1 to disable the ADC TSNS functionality for this channel
0h = TSNS ADC functionality enabled 1h = TSNS ADC functionality is disabled |
| 13 | ISNS_DIS_CH2 | R/W | 0h | Set this bit to 1 to disable ISNS ADC functionality for this channel
0h = ISNS ADC functionality enabled 1h = ISNS ADC functionality is disabled |
| 12-11 | OL_ON_THLD_CH2 | R/W | 0h | Sets the open load detection threshold in the on state. 2 bits to set the open load detection threshold, not implemented in current silicon revision
0h = TBD 1h = TBD 2h = TBD 3h = TBD |
| 10 | ISNS_SCALE_CH2 | R/W | 0h | Turns on 8x scaling of voltage input to the ADC to improve the current sense resolution
0h = ADC input voltage scale equals 1 1h = ADC input voltage scale equals 8 |
| 9 | OL_ON_EN_CH2 | R/W | 0h | Turns on a more accurate open load detection in the on state with KSNS ratio scaled to lower value. This will set the FET into high Rdson mode therefore this cannot be enabled if there is an existing fault on the channel or the current is too high
0h = KSNS ratio and FET Rdson unchanged 1h = Enable more accurate Open Load Detection with a lower KSNS ratio and higher Rdson |
| 8-7 | OL_SVBB_BLANK_CH2 | R/W | 0h | Sets the blanking time for open load (ON-state and OFF-state) and the short_to_VBB faults before the fault is registered.
0h = Blanking time is 0.4 ms 1h = Blanking time is 1.0 ms 2h = Blanking time is 2.0 ms 3h = Blanking time is 4.0 ms |
| 6-5 | OL_PU_STR_CH2 | R/W | 0h | Sets the pullup current value (at the OUTx pins) by the off-state open load detection circuit.
0h = I_pu is 32 uA 1h = I_pu is 64 uA 2h = I_pu is 128 uA 3h = I_pu is 256 uA |
| 4 | OL_OFF_EN_CH2 | R/W | 0h | Turns on the pull up to see if there is an open load in the off state. Cannot bet set high if channel is on or fault exists |
| 3 | SVBB_EN_CH2 | R/W | 0h | Turns on the pull down to see if there is a short to VBB in the off state. Cannot bet set high if channel is on or fault exists |
| 2 | LATCH_CH2 | R/W | 0h | If fault occurs that channel shuts down, this bit sets if the channel auto retries or latches off
0h = Auto retry after tRETRY and Thys 1h = latch off until SW_STATE register is written to again |
| 1-0 | SLRT_CH2 | R/W | 2h | Slew Rate set for ouput of CH1. 4 different slew rate values for adjustable slew rate per electrical characteristics table |
ADC_RESULT_CH2_I is shown in Table 8-30.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | ISNS_RDY_CH2 | R | 0h | Making sure the ADC conversion is new from the last time this was read |
| 9-0 | ADC_RESULT_CH2_I | R | 0h | ADC result (10-bits) from the conversion of the current in CH2 |
ADC_RESULT_CH2_T is shown in Table 8-31.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | TSNS_RDY_CH2 | R | 0h | Making sure the ADC conversion is new from the last time this was read |
| 9-0 | ADC_RESULT_CH2_T | R | 0h | ADC result (10-bits) from the conversion of the temperature in CH2 |
ADC_RESULT_CH2_V is shown in Table 8-32.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | VSNS_RDY_CH2 | R | 0h | Making sure the ADC conversion is new from the last time this was read |
| 9-0 | ADC_RESULT_CH2_V | R | 0h | ADC result (10-bits) from the conversion of the output voltage in CH2 |
I2T_CONFIG_CH2 is shown in Table 8-33.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | TCLDN_CH2 | R/W | 0h | 2bits to Set cool down time for I2T functionality for Channel 2 (time to retry after I2T shutdown.
0h = Latch mode (or no retry) 1h = 0.8 s 2h = 2.0 s 3h = 4.0 s |
| 13-11 | RESERVED | R | 0h | Reserved |
| 10-9 | SWCL_DLY_TMR_CH2 | R/W | 0h | 2-bits to set delayed turn-off timer for Channel 2. Sets the time after which the channel shuts down when the current exceeds ISWCL.
0h = 0.2 ms 1h = 0.4 ms 2h = 1.0 ms 3h = 2.0 ms |
| 8-7 | ISWCL_CH2 | R/W | 0h | 2-bits to set delayed turn-off current threshold value for I2T functionality for Channel 2. The threshold should be set below the maximum current sensed with the sense resistor chosen. The current threshold assumes a sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs
0h = 19.55 1h = 17.6 2h = 16.05 3h = 13.3 |
| 6-3 | I2T_TRIP_CH2 | R/W | 0h | 4-bits to Set Trip value for I2T functionality for Channel 1. Assumes sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs and the threshold changes by the square of the current.
0h = 8.8 A2s 1h = 13.1 A2s 2h = 26.3 A2s 3h = 39.4 A2s 4h = 52.5 A2s 5h = 65.6 A2s 6h = 78.8 A2s 7h = 91.9 A2s 8h = 109.4 A2s 9h = 126.9 A2s Ah = 144.4 A2s Bh = 166.3 A2s Ch = 192.5 A2s Dh = 218.8 A2s Eh = 262.5 A2s Fh = 350 A2s |
| 2-0 | NOM_CUR_CH2 | R/W | 0h | 3 bits to set the nomial current value of Channel 2. Assumes sense resistor of 700 Ωs, otherwise scale the current with the resistor value relative to 700 Ωs
0h = 4.0 A 1h = 5.0 A 2h = 5.7 A 3h = 6.5 A 4h = 7.5 A 5h = 9.0 A 6h = 12.0 A 7h = 15.0 A |