JAJSF84B December 2008 – May 2018 TPS650250
PRODUCTION DATA.
The TPS650250 incorporates three synchronous step-down converters operating typically at 2.25 MHz fixed frequency PWM (Pulse Width Modulation) at moderate to heavy load currents. At light load currents the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation). VDCDC1 delivers up to 1.6 A, VDCDC2 and VDCDC3 are capable of delivering up to 0.8 A of output current.
The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The pins can either be connected to GND, VCC or to a resistor divider between the output voltage and GND. The VDCDC1 converter defaults to 2.8 V or 3.3 V depending on the DEFDCDC1 configuration pin, if DEFDCDC1 is tied to ground the default is 2.80 V, if it is tied to VCC the default is 3.3 V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. Reference the section on Output Voltage Selection for details on setting the output voltage range.
The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin, if DEFDCDC2 is tied to ground the default is 1.8 V, if it is tied to VCC the default is 2.5 V. When the DEFDCDC2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.
On the DEFDCDC3 pin for the VDCDC3 converter, a resistor divider must be connected to set the output voltage. This pin does not accept a logic signal like DEFDCDC1 or DEFDCDC2. The value for the resistor divider can be changed during operation, so voltage scaling can be implemented by changing the resistor value.
During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch.
The three DC-DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A 180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the VDCDC2 converter from 3.7 V to 2.5 V and the VDCDC3 converter from 3.7 V to 1.5 V.