JAJSF84B December   2008  – May 2018 TPS650250

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     詳細ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Dissipation Ratings
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics VDCDC1
    8. 6.8  Electrical Characteristics VDCDC2
    9. 6.9  Electrical Characteristics VDCDC3
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Step-Down Converters, VDCDC1, VDCDC2 AND VDCDC3
      2. 7.3.2 Power Save Mode Operation
      3. 7.3.3 Soft Start
      4. 7.3.4 100% Duty Cycle Low Dropout Operation
      5. 7.3.5 Low Dropout Voltage Regulators
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 PWRFAIL
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Configuration For The Samsung Processor S3C6400-533MHz
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection for the DCDC Converters
        2. 8.2.3.2 Output Capacitor Selection
        3. 8.2.3.3 Input Capacitor Selection
        4. 8.2.3.4 Output Voltage Selection
        5. 8.2.3.5 Voltage Change on VDCDC3
        6. 8.2.3.6 Vdd_alive Output
        7. 8.2.3.7 LDO1 and LDO2
        8. 8.2.3.8 Vcc-Filter
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.3.2 Output Capacitor Selection

The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the TPS650250x allows the use of small ceramic capacitors with a typical value of 10 µF for each converter, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. Refer to Table 5 for recommended components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. For completeness, the RMS ripple current is calculated as:

Equation 5. TPS650250 q5_irmsc_lvs774.gif

At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor:

Equation 6. TPS650250 q6_deltav_lvs774.gif

Where the highest output voltage ripple occurs at the highest input voltage, Vin.

At light load currents the converters operate in Power Save Mode and output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. Typical output voltage ripple is less than 1% of the nominal output voltage.