JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
To start up each converter independently, the device has a separate enable pin for each of the DC-DC converters. In order to enable any converter with its enable pins, the TPS6507x devices need to be in ON-state by pulling PB_IN=LOW or POWER_ON=HIGH. The sequencing option programmed needs to be DCDC_SQ[2..0] = 101.
If EN_DCDC1, EN_DCDC2, EN_DCDC3 are set to high, the corresponding converter starts up with soft start as previously described.
Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the electrical characteristics. In this mode, the high side and low side MOSFETs are turned-off, and the entire internal control circuitry is switched-off. If disabled, the outputs of the DC-DC converters are pulled low by internal 250-Ω resistors, actively discharging the output capacitor. For proper operation the enable pins must be terminated and must not be left floating.
Optionally, there is internal sequencing for the DC-DC converters and both LDOs available. Bits DCDC_SQ[0..2] in register CON_CTRL1 define the start-up and shut-down sequence for the DC-DC converters. Depending on the sequencing option, the signal at EN_DCDC1, EN_DCDC2 and EN_DCDC3 are ignored. For automatic internal sequencing, the enable signals which are not used should be connected to GND.
LDO1 and LDO2 will start up automatically as defined in register LDO_CTRL1. See details about the sequencing options in CON_CTRL1. Register Address: 0Dh and LDO_CTRL1. Register Address: 16h.