JAJSFE6I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
This pin is the ON/OFF button for the PMU to leave OFF-state and enter ON-state by pulling this pin to GND. Entering ON-state will first ramp the output voltage of the power path (SYS), load the default register settings and start up the DCDC converters and LDOs with the sequencing defined. In ON-state, the I2C interface is active and the wLED converter can be enabled. The system turns on if PB_IN is pulled LOW for >50 ms (debounce time) AND the output voltage of the power path manager is above the undervoltage lockout voltage (AVDD6 > 3 V). This is for Vbat>3 V OR VAC>3 V OR VUSB>3 V. The default voltage for the undervoltage lockout voltage can be changed with Bits <UVLO1>, <UVLO0> in register CON_CTRL2. The value will be valid until the device was turned off completely by entering Off state. The system turns off if PB_IN is released OR the system voltage falls below the undervoltage lockout voltage of 3 V. This is the case when either the battery voltage drops below 3 V or the input voltage at the pins AC or USB is below 3 V. In order to keep the TPS6507x enabled after PB_IN is released HIGH, there is an input pin called POWER_ON which needs to be pulled HIGH before the PB_IN button is released. POWER_ON=HIGH will typically be asserted by the application processor to keep the PMU in ON-state after the power button at PB_IN is released.
In addition to this, there is a 15-s timer which will drive PGOOD=LOW for 0.5 ms when 15 s are expired. The 15-s timer is enabled again when PB_IN is released HIGH. If PB_IN is pulled LOW for 30 s continuously, PGOOD will be driven LOW only once after the first 15 s. When PGOOD is driven LOW due to PB_IN=low for 15 s, all registers in TPS6507x are set to their default value. See Figure 34.