JAJSE66E June   2017  – December 2022 TPS650864

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Total Current Consumption
    6. 7.6  Electrical Characteristics: Reference and Monitoring System
    7. 7.7  Electrical Characteristics: Buck Controllers
    8. 7.8  Electrical Characteristics: Synchronous Buck Converters
    9. 7.9  Electrical Characteristics: LDOs
    10. 7.10 Electrical Characteristics: Load Switches
    11. 7.11 Digital Signals: I2C Interface
    12. 7.12 Digital Input Signals (CTLx)
    13. 7.13 Digital Output Signals (IRQB, GPOx)
    14. 7.14 Timing Requirements
    15. 7.15 Switching Characteristics
    16. 7.16 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  TPS6508640 Design and Settings
      1. 8.3.1 TPS6508640 OTP Summary
    4. 8.4  TPS65086401 Design and Settings
      1. 8.4.1 TPS65086401 OTP Summary
      2.      31
    5. 8.5  TPS6508641 Design and Settings
      1. 8.5.1 TPS6508641 OTP Summary
    6. 8.6  TPS65086470 Design and Settings
      1. 8.6.1 TPS65086470 OTP Summary
    7. 8.7  SMPS Voltage Regulators
      1. 8.7.1 Controller Overview
      2. 8.7.2 Converter Overview
      3. 8.7.3 DVS
      4. 8.7.4 Decay
      5. 8.7.5 Current Limit
    8. 8.8  LDOs and Load Switches
      1. 8.8.1 VTT LDO
      2. 8.8.2 LDOA1–LDOA3
      3. 8.8.3 Load Switches
    9. 8.9  Power Goods (PGOOD or PG) and GPOs
    10. 8.10 Power Sequencing and VR Control
      1. 8.10.1 CTLx Sequencing
      2. 8.10.2 PG Sequencing
      3. 8.10.3 Enable Delay
      4. 8.10.4 Power-Up Sequence
      5. 8.10.5 Power-Down Sequence
      6. 8.10.6 Sleep State Entry and Exit
      7. 8.10.7 Emergency Shutdown
    11. 8.11 Device Functional Modes
      1. 8.11.1 Off Mode
      2. 8.11.2 Standby Mode
      3. 8.11.3 Active Mode
    12. 8.12 I2C Interface
      1. 8.12.1 F/S-Mode Protocol
    13. 8.13 Register Maps
      1. 8.13.1  Register Map Summary
      2. 8.13.2  DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
      3. 8.13.3  DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
      4. 8.13.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 8.13.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 8.13.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 8.13.7  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
      8. 8.13.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
      9. 8.13.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
      10. 8.13.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
      11. 8.13.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
      12. 8.13.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
      13. 8.13.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
      14. 8.13.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
      15. 8.13.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
      16. 8.13.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
      17. 8.13.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
      18. 8.13.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
      19. 8.13.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
      20. 8.13.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
      21. 8.13.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
      22. 8.13.22 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      23. 8.13.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
      24. 8.13.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
      25. 8.13.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
      26. 8.13.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
      27. 8.13.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
      28. 8.13.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
      29. 8.13.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
      30. 8.13.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
      31. 8.13.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
      32. 8.13.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
      33. 8.13.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
      34. 8.13.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
      35. 8.13.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
      36. 8.13.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
      37. 8.13.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h) [reset = X]
      38. 8.13.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
      39. 8.13.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
      40. 8.13.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
      41. 8.13.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
      42. 8.13.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
      43. 8.13.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
      44. 8.13.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
      45. 8.13.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
      46. 8.13.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
      47. 8.13.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
      48. 8.13.48 MISCSYSPG Register (offset = ACh) [reset = X]
        1. 8.13.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
      49. 8.13.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
      50. 8.13.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
      51. 8.13.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
      52. 8.13.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]
      53. 8.13.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]
      54. 8.13.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      55. 8.13.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      56. 8.13.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Controller Design Procedure
          1. 9.2.2.1.1 Selecting the Inductor
          2. 9.2.2.1.2 Selecting the Output Capacitors
          3. 9.2.2.1.3 Selecting the FETs
          4. 9.2.2.1.4 Bootstrap Capacitor
          5. 9.2.2.1.5 Setting the Current Limit
          6. 9.2.2.1.6 Selecting the Input Capacitors
        2. 9.2.2.2 Converter Design Procedure
          1. 9.2.2.2.1 Selecting the Inductor
          2. 9.2.2.2.2 Selecting the Output Capacitors
          3. 9.2.2.2.3 Selecting the Input Capacitors
        3. 9.2.2.3 LDO Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Layout
        1. 9.2.4.1 Layout Guidelines
        2. 9.2.4.2 Layout Example
      5. 9.2.5 VIN 5-V Application
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Design Procedure
        3. 9.2.5.3 Application Curves
    3. 9.3 Power Supply Coupling and Bulk Capacitors
    4. 9.4 Do's and Don'ts
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 TPS6508641 Design and Settings

The TPS6508641 device is intended to power the lower range of the Xilinx Zynq Ultrascale+ platform. It removes the need for an external 5 V regulator when compared with the TPS65086401 device and also supports a wider variety of Zynq Ultrascale+ power states. Figure 8-9 shows a simple example block diagram for an always-on system, while Figure 8-10 shows a block diagram for full power domain flexibility. See Xilinx's Ultrascale Architecture PCB Design for explanation of the power supply configurations.

GUID-3D5D5E05-49E8-493D-AC41-33F9CDC5AAB0-low.gif
(1) External FETs can be scaled to meet the current requirements of each design; CSD87381P is suitable up to approximately 15 A.
(2) The TPS6508641 is not limited to the ZU2CG - ZU5EG. It can support other Ultrascale+ devices as long as the use case does not exceed the maximum specifications of the TPS6508641.
Figure 8-9 TPS6508641 Always-On Power Map Example
GUID-7486DE63-AFE7-467B-83C8-D85804C2D700-low.gif
(1) External FETs can be scaled to meet the current requirements of each design; CSD87381P is suitable up to approximately 15 A.
(2) The TPS6508641 is not limited to the ZU2CG - ZU5EG. It can support other Ultrascale+ devices as long as the use case does not exceed the maximum specifications of the TPS6508641.
Figure 8-10 TPS6508641 Full Power Domain Flexibility Power Map Example

The power up and power down sequences can be seen in Figure 8-11 and Figure 8-12. Regulators and GPOs are enabled by combination of CTL pins and regulator power good signals.

GUID-E4E56C12-C031-455F-8530-4CFF37F61572-low.gifFigure 8-11 TPS6508641 Power-Up Sequence
GUID-9CAF5FAE-A293-43C4-87E5-8E80ACC171D7-low.gif
(1) Sequence shown assumes CTL3 is high. If CTL3 is set low before this point, these voltage regulators will already be disabled.
(2) Sequence shown assumes CTL5 is high. If CTL5 is set low before this point, these voltage regulators will already be disabled.
Figure 8-12 TPS6508641 Power-Down Sequence
GUID-A27A7684-91E8-4787-831B-CDDBA0602EBE-low.gif Figure 8-13 TPS6508641 Low Power States

The TPS6508641 device is designed to be able to support always on and full power domain flexibility power modes. The low power states can be omitted if not required.

CTL4 is used to start the primary power sequence and CTL1, CTL3, and CTL5 should all be high initially to complete the power up sequence. For always-on case, CTL3 and CTL5 can be shorted with CTL4.

CTL6 is used to select BUCK3 voltage between BUCK3_VID and BUCK3_SLP_VID register bits. Logic level low will result in 1.2 V while logic level high will result in 1.1 V.

CTL2 is used to enable and disable SWA1 and is independent of the rest of the sequence.

When CTL1 is set low, GPO3 (PS_POR_B) is set low regardless of the power state and has 50 ms delay before going high after CTL1 goes high. It is used as a reset for the Zynq Ultrascale+ device. It can be pulled up to LDO3P3 (3.3 V) or BUCK6 (1.8 V) as preferred with a 10 kΩ resistor and a pushbutton can short this CTL pin to GND when MPSoC reset is desired.

GPO1 and GPO4 are used to control load switches when utilizing the low power modes. The load switches can be omitted for cases where low power modes are not necessary.

VTT LDO voltage used to power VPS_MGTRAVCC is configured to 0.9 V in order to support all variant speeds, including -3E designs. It is within the absolute voltage range and is not expected to impact performance for non-3E designs based on testing with the Ultra96 board. For more information on VPS_MGTRAVCC voltage, see Xilinx's Ultrascale Architecture PCB Design, Table 7-2 MPSoC PS Voltage Matrix by Speed/Temperature Grade.

A summary of the part number specific settings can be seen in Section 8.5.1.