JAJSE66E June   2017  – December 2022 TPS650864

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Total Current Consumption
    6. 7.6  Electrical Characteristics: Reference and Monitoring System
    7. 7.7  Electrical Characteristics: Buck Controllers
    8. 7.8  Electrical Characteristics: Synchronous Buck Converters
    9. 7.9  Electrical Characteristics: LDOs
    10. 7.10 Electrical Characteristics: Load Switches
    11. 7.11 Digital Signals: I2C Interface
    12. 7.12 Digital Input Signals (CTLx)
    13. 7.13 Digital Output Signals (IRQB, GPOx)
    14. 7.14 Timing Requirements
    15. 7.15 Switching Characteristics
    16. 7.16 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  TPS6508640 Design and Settings
      1. 8.3.1 TPS6508640 OTP Summary
    4. 8.4  TPS65086401 Design and Settings
      1. 8.4.1 TPS65086401 OTP Summary
      2.      31
    5. 8.5  TPS6508641 Design and Settings
      1. 8.5.1 TPS6508641 OTP Summary
    6. 8.6  TPS65086470 Design and Settings
      1. 8.6.1 TPS65086470 OTP Summary
    7. 8.7  SMPS Voltage Regulators
      1. 8.7.1 Controller Overview
      2. 8.7.2 Converter Overview
      3. 8.7.3 DVS
      4. 8.7.4 Decay
      5. 8.7.5 Current Limit
    8. 8.8  LDOs and Load Switches
      1. 8.8.1 VTT LDO
      2. 8.8.2 LDOA1–LDOA3
      3. 8.8.3 Load Switches
    9. 8.9  Power Goods (PGOOD or PG) and GPOs
    10. 8.10 Power Sequencing and VR Control
      1. 8.10.1 CTLx Sequencing
      2. 8.10.2 PG Sequencing
      3. 8.10.3 Enable Delay
      4. 8.10.4 Power-Up Sequence
      5. 8.10.5 Power-Down Sequence
      6. 8.10.6 Sleep State Entry and Exit
      7. 8.10.7 Emergency Shutdown
    11. 8.11 Device Functional Modes
      1. 8.11.1 Off Mode
      2. 8.11.2 Standby Mode
      3. 8.11.3 Active Mode
    12. 8.12 I2C Interface
      1. 8.12.1 F/S-Mode Protocol
    13. 8.13 Register Maps
      1. 8.13.1  Register Map Summary
      2. 8.13.2  DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
      3. 8.13.3  DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
      4. 8.13.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 8.13.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 8.13.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 8.13.7  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
      8. 8.13.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
      9. 8.13.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
      10. 8.13.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
      11. 8.13.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
      12. 8.13.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
      13. 8.13.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
      14. 8.13.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
      15. 8.13.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
      16. 8.13.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
      17. 8.13.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
      18. 8.13.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
      19. 8.13.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
      20. 8.13.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
      21. 8.13.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
      22. 8.13.22 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      23. 8.13.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
      24. 8.13.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
      25. 8.13.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
      26. 8.13.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
      27. 8.13.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
      28. 8.13.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
      29. 8.13.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
      30. 8.13.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
      31. 8.13.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
      32. 8.13.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
      33. 8.13.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
      34. 8.13.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
      35. 8.13.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
      36. 8.13.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
      37. 8.13.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h) [reset = X]
      38. 8.13.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
      39. 8.13.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
      40. 8.13.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
      41. 8.13.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
      42. 8.13.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
      43. 8.13.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
      44. 8.13.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
      45. 8.13.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
      46. 8.13.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
      47. 8.13.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
      48. 8.13.48 MISCSYSPG Register (offset = ACh) [reset = X]
        1. 8.13.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
      49. 8.13.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
      50. 8.13.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
      51. 8.13.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
      52. 8.13.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]
      53. 8.13.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]
      54. 8.13.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      55. 8.13.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      56. 8.13.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Controller Design Procedure
          1. 9.2.2.1.1 Selecting the Inductor
          2. 9.2.2.1.2 Selecting the Output Capacitors
          3. 9.2.2.1.3 Selecting the FETs
          4. 9.2.2.1.4 Bootstrap Capacitor
          5. 9.2.2.1.5 Setting the Current Limit
          6. 9.2.2.1.6 Selecting the Input Capacitors
        2. 9.2.2.2 Converter Design Procedure
          1. 9.2.2.2.1 Selecting the Inductor
          2. 9.2.2.2.2 Selecting the Output Capacitors
          3. 9.2.2.2.3 Selecting the Input Capacitors
        3. 9.2.2.3 LDO Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Layout
        1. 9.2.4.1 Layout Guidelines
        2. 9.2.4.2 Layout Example
      5. 9.2.5 VIN 5-V Application
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Design Procedure
        3. 9.2.5.3 Application Curves
    3. 9.3 Power Supply Coupling and Bulk Capacitors
    4. 9.4 Do's and Don'ts
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.9 Electrical Characteristics: LDOs

over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDOA1
VIN Input voltage 4.5 5 5.5 V
VOUT DC output voltage Set by LDOA1_VID[3:0] 1.35 See Section 5 3.3 V
Accuracy IOUT = 0 to 200 mA –2% 2% V
IOUT DC output current 200 mA
ΔVOUT/ΔVIN Line regulation IOUT = 40 mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10 mA to 200 mA –2% 2%
IOCP Overcurrent protection VIN = 5 V, Measured with output shorted to ground 500 mA
VTH_PG Power Good deassertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
tSTARTUP Start-up time Measured from EN = H to reach 95% of final value,
COUT = 4.7 µF		 500 µs
IQ Quiescent current IOUT = 0 A 23 µA
COUT External output capacitance 2.7 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOA1_DISCHG[1:0] = 01 100 Ω
LDOA1_DISCHG[1:0] = 10 190 Ω
LDOA1_DISCHG[1:0] = 11 450 Ω
LDOA2 and LDOA3
VIN Power input voltage VOUT + VDROP(1) 1.8 1.98 V
VOUT LDOA2 DC output voltage Set by LDOA2_VID[3:0] 0.7 See Section 5 1.5 V
LDOA3 DC output voltage Set by LDOA3_VID[3:0] 0.7 See Section 5 1.5 V
DC output voltage accuracy IOUT = 0 to 600 mA –2% 3%
IOUT DC output current 600 mA
VDROP Dropout voltage VOUT = 0.99 × VOUT_NOM,
IOUT = 600 mA		 350 mV
ΔVOUT/ΔVIN Line regulation IOUT = 300 mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10 mA to 600 mA –2% 2%
IOCP Overcurrent protection Measured with output shorted to ground 0.65 1.25 A
VTH_PG Power Good assertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
tSTARTUP Start-up time Measured from EN = H to reach 95% of final value, COUT = 4.7 µF 500 µs
IQ Quiescent current IOUT = 0 A 20 µA
PSRR Power supply rejection ratio f = 1 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF – 4.7 µF		 48 dB
f = 10 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF – 4.7 µF		 30 dB
COUT External output capacitance 2.2 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOA[2,3]_DISCHG[1:0] = 01 80 Ω
LDOA[2,3]_DISCHG[1:0] = 10 180
LDOA[2,3]_DISCHG[1:0] = 11 475
VTT LDO
VIN Power input voltage 1.2 3.3 V
VOUT DC output voltage VIN = 1.2 V, Measured at VTTFB pin VIN / 2 V
DC output voltage accuracy Relative to VIN / 2, IOUT ≤ 10 mA,
1.1 V ≤ VIN ≤ 1.35 V		 –10 10 mV
Relative to VIN / 2, IOUT ≤ 500 mA,
1.1 V ≤ VIN ≤ 1.35 V		 –25 25
IOUT DC Output Current (Rms Value Over Operation) 1.1 V ≤ VIN ≤ 1.5 V –500 0 500 mA
Pulsed Current (Duty Cycle Limited to Remain Below DC Rms Specification) source(+) and sink(–): IOCP = 0.95 A, 1.1 V ≤ VIN ≤ 1.5 V –500 500 mA
source(+) and sink(–): IOCP = 1.8 A, 1.1 V ≤ VIN ≤ 1.5 V –1800 1800
ΔVOUT/ΔIOUT Load regulation Relative to VIN / 2, IOUT ≤ 10 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –10 10 mV
Relative to VIN / 2, IOUT ≤ 500 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –20 20
Relative to VIN / 2, IOUT ≤ 1200 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –30 30
Relative to VIN / 2, IOUT ≤ 1800 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –40 40
ΔVOUT_TR Load transient regulation DC + AC at sense point, 1.1 V ≤ VIN ≤ 1.5 V,
(IOUT = 0 to 350 mA and 350 mA to 0) AND
(0 to –350 mA and –350 mA to 0) with 1 µs of rise and fall time
COUT = 40 µF		 –5% 5%
IOCP Overcurrent protection Measured with output shorted to ground: OTPs with VTT ILIM = 0.95 A 0.95 A
Measured with output shorted to ground: OTPs with VTT ILIM = 1.8 A 1.8
VTH_PG Power Good deassertion threshold in percentage of target VOUT VOUT rising 110%
VOUT falling 95%
VTH_HYS_PG Power Good reassertion hysteresis entering back into VTH_PG 5%
IQ Total ground current VIN = 1.2 V, IOUT = 0 A 240 µA
ILKG OFF leakage current VIN = 1.2 V, disabled 1 µA
CIN External input capacitance 10 µF
COUT External output capacitance 35 µF
RDIS Output auto-discharge resistance VTT_DISCHG = 0 1000 kΩ
VTT_DISCHG = 1 60 80 100 Ω
(1) The minimum value must be equal to or greater than 1.62 V.