JAJSE66E June   2017  – December 2022 TPS650864

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Total Current Consumption
    6. 7.6  Electrical Characteristics: Reference and Monitoring System
    7. 7.7  Electrical Characteristics: Buck Controllers
    8. 7.8  Electrical Characteristics: Synchronous Buck Converters
    9. 7.9  Electrical Characteristics: LDOs
    10. 7.10 Electrical Characteristics: Load Switches
    11. 7.11 Digital Signals: I2C Interface
    12. 7.12 Digital Input Signals (CTLx)
    13. 7.13 Digital Output Signals (IRQB, GPOx)
    14. 7.14 Timing Requirements
    15. 7.15 Switching Characteristics
    16. 7.16 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  TPS6508640 Design and Settings
      1. 8.3.1 TPS6508640 OTP Summary
    4. 8.4  TPS65086401 Design and Settings
      1. 8.4.1 TPS65086401 OTP Summary
      2.      31
    5. 8.5  TPS6508641 Design and Settings
      1. 8.5.1 TPS6508641 OTP Summary
    6. 8.6  TPS65086470 Design and Settings
      1. 8.6.1 TPS65086470 OTP Summary
    7. 8.7  SMPS Voltage Regulators
      1. 8.7.1 Controller Overview
      2. 8.7.2 Converter Overview
      3. 8.7.3 DVS
      4. 8.7.4 Decay
      5. 8.7.5 Current Limit
    8. 8.8  LDOs and Load Switches
      1. 8.8.1 VTT LDO
      2. 8.8.2 LDOA1–LDOA3
      3. 8.8.3 Load Switches
    9. 8.9  Power Goods (PGOOD or PG) and GPOs
    10. 8.10 Power Sequencing and VR Control
      1. 8.10.1 CTLx Sequencing
      2. 8.10.2 PG Sequencing
      3. 8.10.3 Enable Delay
      4. 8.10.4 Power-Up Sequence
      5. 8.10.5 Power-Down Sequence
      6. 8.10.6 Sleep State Entry and Exit
      7. 8.10.7 Emergency Shutdown
    11. 8.11 Device Functional Modes
      1. 8.11.1 Off Mode
      2. 8.11.2 Standby Mode
      3. 8.11.3 Active Mode
    12. 8.12 I2C Interface
      1. 8.12.1 F/S-Mode Protocol
    13. 8.13 Register Maps
      1. 8.13.1  Register Map Summary
      2. 8.13.2  DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
      3. 8.13.3  DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
      4. 8.13.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 8.13.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 8.13.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 8.13.7  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
      8. 8.13.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
      9. 8.13.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
      10. 8.13.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
      11. 8.13.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
      12. 8.13.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
      13. 8.13.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
      14. 8.13.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
      15. 8.13.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
      16. 8.13.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
      17. 8.13.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
      18. 8.13.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
      19. 8.13.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
      20. 8.13.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
      21. 8.13.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
      22. 8.13.22 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      23. 8.13.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
      24. 8.13.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
      25. 8.13.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
      26. 8.13.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
      27. 8.13.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
      28. 8.13.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
      29. 8.13.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
      30. 8.13.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
      31. 8.13.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
      32. 8.13.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
      33. 8.13.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
      34. 8.13.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
      35. 8.13.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
      36. 8.13.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
      37. 8.13.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h) [reset = X]
      38. 8.13.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
      39. 8.13.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
      40. 8.13.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
      41. 8.13.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
      42. 8.13.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
      43. 8.13.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
      44. 8.13.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
      45. 8.13.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
      46. 8.13.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
      47. 8.13.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
      48. 8.13.48 MISCSYSPG Register (offset = ACh) [reset = X]
        1. 8.13.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
      49. 8.13.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
      50. 8.13.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
      51. 8.13.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
      52. 8.13.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]
      53. 8.13.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]
      54. 8.13.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      55. 8.13.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      56. 8.13.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Controller Design Procedure
          1. 9.2.2.1.1 Selecting the Inductor
          2. 9.2.2.1.2 Selecting the Output Capacitors
          3. 9.2.2.1.3 Selecting the FETs
          4. 9.2.2.1.4 Bootstrap Capacitor
          5. 9.2.2.1.5 Setting the Current Limit
          6. 9.2.2.1.6 Selecting the Input Capacitors
        2. 9.2.2.2 Converter Design Procedure
          1. 9.2.2.2.1 Selecting the Inductor
          2. 9.2.2.2.2 Selecting the Output Capacitors
          3. 9.2.2.2.3 Selecting the Input Capacitors
        3. 9.2.2.3 LDO Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Layout
        1. 9.2.4.1 Layout Guidelines
        2. 9.2.4.2 Layout Example
      5. 9.2.5 VIN 5-V Application
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Design Procedure
        3. 9.2.5.3 Application Curves
    3. 9.3 Power Supply Coupling and Bulk Capacitors
    4. 9.4 Do's and Don'ts
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

Figure 6-1 shows the 64-pin RSK Plastic Quad Flatpack No-Lead package.

The thermal pad must be connected to the system power ground plane.
Figure 6-1 64-Pin RSK VQFN With Exposed Thermal Pad (Top View)
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
SMPS REGULATORS
1 FBGND2 I Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output capacitor. Connect to ground when not in use.
2 FBVOUT2 I Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output capacitor. Connect to ground when not in use.
3 DRVH2 O High-side gate driver output for BUCK2 controller. Leave floating when not in use.
4 SW2 I Switch node connection for BUCK2 controller. Connect to ground when not in use.
5 BOOT2 I Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and SW2 pin. Leave floating when not in use.
6 PGNDSNS2 I Power GND connection for BUCK2. Connect to ground terminal of external low-side FET. Connect to ground when not in use.
7 DRVL2 O Low-side gate driver output for BUCK2 controller. Leave floating when not in use.
8 DRV5V_2_A1 I 5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on board to LDO5P0 pin typically. Bypass not required if BUCK2 and LDOA1 are not in use.
10 LX3 O Switch node connection for BUCK3 converter. Leave floating when not in use.
11 PVIN3 I Power input to BUCK3 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if BUCK3 is not in use.
12 FB3 I Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor. Connect to ground when not in use.
20 LX5 O Switch node connection for BUCK5 converter. Leave floating when not in use.
21 PVIN5 I Power input to BUCK5 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if BUCK5 is not in use.
22 FB5 I Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor. Connect to ground when not in use.
23 FB4 I Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor. Connect to ground when not in use.
24 PVIN4 I Power input to BUCK4 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if BUCK4 is not in use.
25 LX4 O Switch node connection for BUCK4 converter. Leave floating when not in use.
29 FBVOUT1 I Remote feedback sense for BUCK1 controller. Connect to positive terminal of output capacitor. Connect to ground when not in use.
30 ILIM1 I Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET. Connect to ground when BUCK1 not in use.
33 DRVH1 O High-side gate driver output for BUCK1 controller. Leave floating when not in use.
34 SW1 I Switch node connection for BUCK1 controller. Connect to ground when not in use.
35 BOOT1 I Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and SW1 pin. Leave floating when not in use.
36 PGNDSNS1 I Power GND connection for BUCK1. Connect to ground terminal of external low-side FET. Connect to ground when not in use.
37 DRVL1 O Low-side gate driver output for BUCK1 controller. Leave floating when not in use.
38 DRV5V_1_6 I 5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on board to LDO5P0 pin typically. Bypass not required if BUCK1 and BUCK6 are not in use.
39 DRVL6 O Low-side gate driver output for BUCK6 controller. Leave floating when not in use.
40 PGNDSNS6 I Power GND connection for BUCK6. Connect to ground terminal of external low-side FET. Connect to ground when not in use.
41 BOOT6 I Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and SW6 pin. Leave floating when not in use.
42 SW6 I Switch node connection for BUCK6 controller. Connect to ground when not in use.
43 DRVH6 O High-side gate driver output for BUCK6 controller. Leave floating when not in use.
44 FBVOUT6 I Remote feedback sense for BUCK6 controller and reference voltage for VTT LDO regulation. Connect to positive terminal of output capacitor. Connect to ground when not in use.
45 ILIM6 I Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET. Connect to ground when BUCK6 not in use.
64 ILIM2 I Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET. Connect to ground when BUCK2 not in use.
LDO AND LOAD SWITCHES
9 LDOA1 O LDOA1 output. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
17 SWB1 O Output of load switch B1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
18 PVINSWB1_B2 I Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient performance. Connect to ground when not in use.
19 SWB2 O Output of load switch B2. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
31 SWA1 O Output of load switch A1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
32 PVINSWA1 I Power supply to load switch A1. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient performance. Connect to ground when not in use.
46 PVINVTT I Power supply to VTT LDO. Bypass to ground with a 10-µF (minimum) ceramic capacitor. Bypass not required if VTT LDO is not in use.
47 VTT O Output of load VTT LDO. Bypass to ground with 2× 22-µF (minimum) ceramic capacitors. Leave floating when not in use.
48 VTTFB I Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor. Connect to ground when not in use.
49 LDOA3 O Output of LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
50 PVINLDOA2_A3 I Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Connect to ground when not in use.
51 LDOA2 O Output of LDOA2. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
54 LDO3P3 O Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
56 LDO5P0 O Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
57 V5ANA I Bias used by converters (BUCK3, BUCK4, and BUCK5) for regulation. Must be same supply as PVINx. Also has an internal load switch that connects this pin to LDO5P0 pin if 5-V is used. Bypass this pin with an optional ceramic capacitor to improve transient performance.
INTERFACE
13 CTL1 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
14 CTL6/SLPENB2 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out of (H) sleep state where their output voltages may be different from those in normal state.
15 IRQB O Open-drain output interrupt pin. Refer to Section 8.13.4, IRQ: PMIC Interrupt Register, for definitions.
16 GPO1 O General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
26 GPO2 O General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
27 GPO3 O General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
28 GPO4 O Open-drain output that can be configured to reflect Power Good status of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
58 CLK I I2C clock
59 DATA I/O I2C data
60 CTL2 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
61 CTL3/SLPENB1 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out of (H) sleep state where their output voltages may be different from those in normal state.
62 CTL4 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
63 CTL5 I Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of this pin.
REFERENCE
52 AGND — Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of VREF capacitor.
53 VREF O Band-gap reference output. Stabilize it by connecting a 100-nF (typical) ceramic capacitor between this pin and quiet ground.
55 VSYS I System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a 1-µF (typical) ceramic capacitor.
THERMAL PAD
— Thermal pad (PGND) — Connect to PCB ground plane using multiple vias for good thermal and electrical performance.