JAJSGZ1C September 2015 – February 2019 TPS65094
PRODUCTION DATA.
When VSYS crosses below VSYS_UVLO_5V, all Power Good pins are deasserted; after 444 ns (nominal) of delay, all VRs shut down (see Figure 6-12). Upon shutdown, all internal discharge resistors are set to 100 Ω to ensure timely decay of all VR outputs. VSYS crossing above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS and assertion of PMICEN is required to re-enable the VRs.
Other conditions that cause emergency shutdown are the following: