6.3.2 Register Reset Conditions
All registers are reset if any of the following conditions are met:
- VSYS pin voltage drops below 5.4 V
- Falling edge of PMICEN for OTPs where LDOA1 is not "Always On"
- Falling edge of THERMTRIPB while RSMRSTB = 1
- Power fault of any regulator where xx_FLTMSK = 0 (see Section 6.6.27, PWR_FAULT_MASK1 Register, and Section 6.6.28, PWR_FAULT_MASK2 Register)
- PMIC critical temperature shutdown
- Software shutdown (writing 1 to the SDWN bit in the FORCESHUTDN register, see Figure 6-35)
Additionally, BUCK1 and BUCK2 VID registers are reset on the falling edge of SLP_S0IXB and SLP_S3B.