The EN/PB/VSENSE pin is used to enable the PMIC. The pin can be configured in three ways:

• Device enable (EN):
  • This pin needs to be pulled high to enable the device. Pulling this pin low disables the device.
  • The deglitch-time of the EN-pin is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
  • The power-up sequence starts if the EN input is above the V_IL-threshold low for the configured t_{DEGL_EN_Rise}.
  • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
  • The power-down sequence starts if the EN input is below the V_IH-threshold for t_{DEGL_EN_Fall}.
  • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence if EN input is still above the V_IH-threshold. (EN considered level-sensitive)
  • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence if EN input is still above the V_IH-threshold. (EN considered level-sensitive)
• Push-Button (PB):
  • The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a momentary switch to ground and an external pullup resistor.
  • The hold-time of the push-button is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
  • The power-up sequence starts if the PB input is below the V_IL-threshold low for the configured t_{PB_ON}.
  • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
  • The PB pin has a rising-edge deglitch t_{PB_RISE_DEGL} to filter bouncing of the switch
  • The power-down sequence starts if the PB input is held low for t_{PB_OFF}-time (not configurable).
  • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence without a PB-press.
  • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence without a PB-press.
  • A push-button press is only recognized after VSYS is above VSYS_POR-threshold or the PB must be held long enough after VSYS is above VSYS_POR-threshold.
  • Following bits in the signify the PB-press events:
    • PB_FALLING_EDGE_DETECTED: PB was pressed for a time-interval longer than t_{PB_INT_DEGL} since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit MASK_INT_FOR_PB='0'). Write W1C to clear.
    • PB_RISING_EDGE_DETECTED: PB was released for a time-interval longer than t_{PB_INT_DEGL} since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit MASK_INT_FOR_PB='0'). Write W1C to clear.
    • PB_REAL_TIME_STATUS: Deglitched (t_{PB_INT_DEGL}) real-time status of PB pin. Valid only when EN/PB/VSENSE pin is configured as PB. This bit does not assert the nINT pin.

• Power-fail comparator input (VSENSE):
  • Connected to a resistor divider from the supply-line of the pre-regulator, this pin can be used to sense the supply-voltage to the pre-regulator.
  • The deglitch-time of the VSENSE-pin is configurable by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.
  • Power-up is gated by VSYS being above the VSYS_{POR_Rising}-threshold and the VSENSE input is above the V_VSENSE-threshold (not deglitched)
  • The power-up sequence starts if the VSENSE input rises above V_VSENSE.
  • To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert the nINT pin. Write W1C to clear the bit.
  • The power-down sequence starts if the VSENSE input falls below the V_VSENSE-threshold for t_{DEGL_VSENSE_Fall}, to avoid an un-sequenced power-off due to the loss of VSYS-supply-voltage.
  • In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power-up sequence if VSENSE input is still above the V_VSENSE-threshold.
  • In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required. The device automatically executes the power-up sequence if VSENSE input is still above the V_VSENSE-threshold.
• OFF-request by I2C-command
  • An OFF-request can also be triggered by an I2C-command to I2C_OFF_REQ in MFP_CTRL register.
  • After such an OFF-request, a new ON-request is required:
    • In case of EN-configuration, the EN input requires a rising edge (EN considered edge-sensitive)
    • In case of PB-configuration, the PB needs to be pressed for a valid ON-request
    • In case of VSENSE-configuration, the VSENSE input requires a rising edge (VSENSE considered edge-sensitive). This can be done by power cycling the pre-regulator.
    • The falling-edge deglitch time for EN or VSENSE configuration t_{DEGL_EN/VSENSE_I2C} is shorter than the deglitch-time for pin-induced OFF-requests (t_{DEGL_EN_Fall} and t_{DEGL_VSENSE_Fall}). The deglitch-times for PB-configuration remain.

• First Supply detection (FSD)
  • First Supply detection (FSD) allows power-up as soon as supply voltage is applied, even if EN/PB/VSENSE pin is at OFF_REQ status.
  • FSD can be used in combination with any ON-request configuration, EN, PB or VSENSE.
  • FSD can be enabled by setting PU_ON_FSD bit in MFP_2_CONFIG.
  • At first power-up the EN/PB/VSENSE pin is treated as if the pin had a valid ON request.
  • Once VSYS is above the VSYS_{POR_Rising}-threshold, the PMIC
    • loads the EEPROM
    • enters INITIALIZE state
    • perform the discharge-check
    • initiates the power-up-sequence, regardless of the EN/PB/VSENSE-pin-state.
  • To signify the power-up based on FSD, the device sets bit POWER_UP_FROM_FSD in POWER_UP_STATUS_REG register. The nINT-pin does not toggle based on this bit. Write W1C to clear the bit.
  • Thereafter, the EN/PB/VSENSE-pin is treated as if the pin had a valid ON-request, until we enter ACTIVE state (at the expiration of the last slot in the power-up-sequence).
  • After that the device adheres to post-deglitch EN/PB/VSENSE-pin-status: if pin status has changed prior to entering ACTIVE state or in ACTIVE state, the device does adhere to the pin state. For example, if the EN/PB/VSENSE-pin is configured for EN, the device does power down in case the EN-pin is low (for longer than the deglitch time) at the time the device enters ACTIVE state.
  • The duration for how long the ON-request is considered valid, regardless of the pin-state, can be controlled by length of nRSTOUT slot (and empty slots thereafter), as the PMIC enters ACTIVE state only after the last slot of the sequence expired.