JAJSH18A March 2019 – September 2019 TPS7A78
The power-good (PG) circuit monitors the VLDO_OUT voltage to indicate the status of the LDO output voltage. PG is pulled low until VLDO_OUT reaches its proper regulate voltage level, then PG is released and allowed to be pulled high. If VLDO_OUT falls below the VIT(PG_FALLING) threshold, PG is asserted low to indicate the LDO output voltage is not in regulation. PG pin low assertion can happen during an overcurrent event or a short-circuit fault.
PG can be used to release the reset pin of a microcontroller. The PG pin must be pulled up to a DC rail such as VLDO_OUT.
Use the recommended pullup resistor value specified in the Electrical Characteristics table for the PG pin. The functionality of the power-good detection pin has no effect on the internal control logic other than to indicate the state of the output voltage. If this function is not used, connect the PG pin to the device GND pins reference.
An external DC rail can also be used to pull up the PG pin signal via a pullup resistor only when the external DC rail shares the same reference GND with the TPS7A78 GND and the absolute maximum voltage of the PG pin is not exceeded.