JAJSH18A March 2019 – September 2019 TPS7A78
Using the device power-fail detection feature is optional as indicated in Figure 14 and Figure 15. The PFD pin is an analog voltage input to an internal comparator that drives the open-drain PF output. The resistor divider consisting of R1 and R2 can be used to set the minimum VSCIN voltage that triggers the PF output. Regardless of whether an AC or DC supply is used, the PF output triggers when the supply fails to maintain the VSCIN voltage above VSCIN (MIN). Equation 22 gives the calculation of the R1 – R2 resistor divider that sets the PF pin trigger point.
Equation 23 calculates the VSCIN (MIN) voltage.
Set R1 as close as possible to the maximum value specified in the Recommended Operating Conditions table. This high R1 value limits the power used by the resistors, then calculates the value of R2. Choose the closest standard resistor value for R2. Optionally, because the PFD pin is a high-impedance node, add a 10-pF capacitor in parallel with the R2 resistors to reduce noise coupling into VPFD.
Pull up the PF pin to a DC rail, such as VLDO_IN, so that a microcontroller can monitor the PF signal as an early power-fail warning to trigger the switch to a backup power solution or to perform a controlled system shutdown. Pulling up the PF pin to VLDO_IN rather than VLDO_OUT ensures that the PF signal is continuously monitored even if VLDO_OUT is down because of a load-transient event or a short-circuit fault.
An external DC rail can also be used to pullup the PF pin signal via a pullup resistor only if the external DC rail shares a common ground with the device GND pins and the absolute maximum of the PF pin voltage is not exceeded.