JAJSH18A March   2019  – September 2019 TPS7A78

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ハーフブリッジ構成の標準的な回路図
      2.      フルブリッジ構成の標準的な回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active Bridge Control
      2. 8.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations
      3. 8.3.3 4:1 Switched-Capacitor Voltage Reduction
      4. 8.3.4 Undervoltage Lockout Circuits (VUVLO_SCIN) and (VUVLO_LDO_IN)
      5. 8.3.5 Dropout Voltage Regulation
      6. 8.3.6 Current Limit
      7. 8.3.7 Programmable Power-Fail Detection
      8. 8.3.8 Power-Good (PG) Detection
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Dropout Mode
      3. 8.4.3 Disabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended Capacitor Types
      2. 9.1.2 Input and Output Capacitors Requirements
      3. 9.1.3 Startup Behavior
      4. 9.1.4 Load Transient
      5. 9.1.5 Standby Power and Output Efficiency
      6. 9.1.6 Reverse Current
      7. 9.1.7 Switched-Capacitor Stage Output Impedance
      8. 9.1.8 Power Dissipation (PD)
      9. 9.1.9 Estimating Junction Temperature
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Calculating the Cap-Drop Capacitor CS
          1. 9.2.2.1.1 CS Calculations for the Typical Design
        2. 9.2.2.2 Calculating the Surge Resistor RS
          1. 9.2.2.2.1 RS Calculations for the Typical Design
        3. 9.2.2.3 Checking for the Device Maximum ISHUNT Current
          1. 9.2.2.3.1 ISHUNT Calculations for the Typical Design
        4. 9.2.2.4 Calculating the Bulk Capacitor CSCIN
          1. 9.2.2.4.1 CSCIN Calculations for the Typical Design
        5. 9.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection
          1. 9.2.2.5.1 PFD Pin Resistor Divider Calculations for the Typical Design
        6. 9.2.2.6 Summary of the Typical Application Design Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価基板
        2. 12.1.1.2 SIMPLIS モデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PWP Package
14-Pin HTSSOP
Top View

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 SC1– — Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1+ pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
2 SC1+ — Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1– pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
3 SCIN — Rectified DC-voltage pin. Place the capacitor as close to the device as possible; see the Device Functional Modes section for the dual-input power-supply capability and the Calculating the Bulk Capacitor section for the proper capacitor calculation.
4 PFD Input Power-failure detect pin. An analog voltage input compares the reference voltage to a resistor-divided VSCIN voltage to detect a VAC power-failure; see the Recommended Operating Conditions table and the Calculating the PFD Pin Resistor Dividers for Power-Fail Detection section for details.
5 AC+ Power AC-supply line or neutral input to the device after the capacitive-drop (cap-drop) capacitor and surge resistor. Either this pin or the AC– pin must have the cap-drop capacitor and surge resistor in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details.
6 GND Ground Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to the thermal pad at the bottom of the device; see the Layout section for details.
7 AC– Power AC-supply line or neutral input to the device pin after the cap-drop capacitor and surge resistor. Either this pin or the AC+ pin must have the cap-drop capacitor and surge resistor in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details.
8 LDO_OUT Output Regulated DC output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor between this pin and the device GND pins. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for the maximum capacitor value.
9 LDO_IN — Charge-pump output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor between this pin and the device GND pins. This pin is internally driven and must not be driven externally. For optimal performance, connect a capacitor that is 10x the value of CLDO_OUT placed as close to the device as possible. See the Recommended Operating Conditions table for the maximum capacitor value.
10 PF Output Power-fail indicator pin. An open-drain indicator signal indicates if the VAC supply has failed. Pullup this pin through an external resistor to VLDO_IN or to a DC-rail that shares the same GND as the device. The PF pin goes low when VPFD is less than the VIT(PFD,FALLING) threshold, as specified in the Electrical Characteristics table. See the Recommended Operating Conditions table for proper selection of the pullup resistor.
11 PG Output Power-good indication pin. An open-drain indicator signal indicates if the VLDO_OUT surpassed the VIT(PG,RISING) threshold, as specified in the Electrical Characteristics table. Pullup this pin through an external resistor to VLDO_OUT or to a DC rail that shares the same GND as the device. See the Recommended Operating Conditions table for proper selection of the pullup resistor.
12 GND Ground Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to the thermal pad at the bottom of the device; see the Layout section for details.
13 SC2+ — Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2– pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
14 SC2– — Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2+ pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
Thermal pad — Exposed pad of the package. Connect this pad to device ground pins. Connect the thermal pad to a large-area ground plane for best thermal performance.