JAJSH18A March   2019  – September 2019 TPS7A78


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      ハーフブリッジ構成の標準的な回路図
      2.      フルブリッジ構成の標準的な回路図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active Bridge Control
      2. 8.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations
      3. 8.3.3 4:1 Switched-Capacitor Voltage Reduction
      4. 8.3.4 Undervoltage Lockout Circuits (VUVLO_SCIN) and (VUVLO_LDO_IN)
      5. 8.3.5 Dropout Voltage Regulation
      6. 8.3.6 Current Limit
      7. 8.3.7 Programmable Power-Fail Detection
      8. 8.3.8 Power-Good (PG) Detection
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Dropout Mode
      3. 8.4.3 Disabled Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended Capacitor Types
      2. 9.1.2 Input and Output Capacitors Requirements
      3. 9.1.3 Startup Behavior
      4. 9.1.4 Load Transient
      5. 9.1.5 Standby Power and Output Efficiency
      6. 9.1.6 Reverse Current
      7. 9.1.7 Switched-Capacitor Stage Output Impedance
      8. 9.1.8 Power Dissipation (PD)
      9. 9.1.9 Estimating Junction Temperature
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Calculating the Cap-Drop Capacitor CS
          1. CS Calculations for the Typical Design
        2. Calculating the Surge Resistor RS
          1. RS Calculations for the Typical Design
        3. Checking for the Device Maximum ISHUNT Current
          1. ISHUNT Calculations for the Typical Design
        4. Calculating the Bulk Capacitor CSCIN
          1. CSCIN Calculations for the Typical Design
        5. Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection
          1. PFD Pin Resistor Divider Calculations for the Typical Design
        6. Summary of the Typical Application Design Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 評価基板
        2. SIMPLIS モデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報



Input and Output Capacitors Requirements

All the capacitors illustrated in Figure 14 or Figure 15 are required for proper operation. The value of CS required to support the application current is obtained from the Calculating the Cap-Drop Capacitor CS section. The chosen CS capacitor must tolerate the peak VAC supply voltage of the application and meet the required safety requirements.

Choosing an a larger value of the CS capacitor than required has an adverse effect on the standby power consumption; however, capacitance reduction over long-term service is inevitable and must be considered when selecting the value of CS. A ceramic capacitor can be used as CS in designs for lower AC supply voltages, but the capacitor voltage rating must be appropriate to the application.

For switching capacitors CSC1 and CSC2, select the minimum-required capacitor values and voltage ratings specified in the Recommended Operating Conditions table. Using too large of a capacitor for the switching capacitors is not recommended because a large capacitor lengthens the start-up time and load transient recovery time of the entire solution. Keep the switching capacitors as close to the device as possible to eliminate any unwanted trace inductance.

For the bulk capacitor CSCIN, use the minimum required capacitor value obtained from the Calculating the Bulk Capacitor CSCIN section and increase that value based on the expected capacitor degradation resulting from aging and operating conditions. Accounting for capacitor degradation is especially important if a relatively low life expectancy of the capacitor is expected when an electrolytic capacitor is used. If the application requires an extended hold-up time, the values of the CSCIN or CLDO_IN capacitors can be increased as long as the maximum capacitor values specified in the Recommended Operating Conditions table are not exceeded. Using a significantly larger values of CSCIN or CLDO_IN has an adverse effect on the startup time of the solution.

For the CLDO_OUT capacitor, maintain a 10:1 ratio between CLDO_IN and CLDO_OUT for applications using the maximum load current. For lesser load currents, the minimum required CLDO_OUT and CLDOU_IN capacitors are sufficient. For optimum performance, place all capacitors as close as possible to the device.