JAJSSS6 January   2024 TPS7H3014-SP

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 7.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 7.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 7.3.2 SENSEx Inputs
        1. 7.3.2.1 VTH_SENSEX and VONx
        2. 7.3.2.2 IHYS_SENSEx and VOFFx
        3. 7.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 7.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 7.3.4 User-Programmable TIMERS
        1. 7.3.4.1 DLY_TMR
        2. 7.3.4.2 REG_TMR
      5. 7.3.5 UP and DOWN
      6. 7.3.6 FAULT
      7. 7.3.7 State Machine
    4. 7.4 Daisy Chain
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Self Contained – Sequence UP and DOWN
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 8.2.1.2.2 UP and DOWN Thresholds
          3. 8.2.1.2.3 SENSEx Thresholds
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2.3 Top and Bottom Resistive Divider Design Equations

At the system level the designer knows (or selects) the VONx and VOFFx levels. Usually these voltages are selected as percentages of the nominal rail voltage (VOUTx) being monitored. Knowing this information, we can calculate the resistive divider components values (RTOPx and RBOTTOMx) for the desired target levels. Using Equation 4 and Equation 5 we can calculate the top resistor as:

Equation 13. R T O P x   =   V O N x - V O F F x I H Y S _ S E N S E x

From Equation 1 we can calculate the bottom resistor as:

Equation 14. R B O T T O M x   =   R T O P x × V T H _ S E N S E x V O N x - V T H _ S E N S E x

It's important to notice that the larger the separation between VONx and VOFFx (referred as VHYSx), the bigger the error in the off voltage. Figure 7-4 shows a plot of the error in the VOFFx for different hysteresis voltages (VHYSx = VONx – VOFFx). The plot is created for three different VON voltages (or percentages of the nominal output voltage: 90, 95, and 97% ) and two different output voltages (0.8V and 28V). As can be observed, the output voltage has very little impact on the off voltage error (differences cannot be appreciated on the plot). The error (in percent) can go from approximately 1% (at VHYS = 3%) to around 2.6% (at VHYS = 80%).

GUID-20230316-SS0I-2FQ0-XDWB-RM3DFP7RWDFC-low.svg Figure 7-4 VOFFx Error vs VHYS
A. This plot does not includes the error on the VOFFx due to the difference between the calculated top and bottom resistors using Equation 13 and Equation 14 and the actual resistance values that a designer can procure.
B. The resistor tolerance used for the calculation is 0.1%, VTH_SENSEx accuracy is 1%, and the IHYS_SENSEx accuracy is 3%.
C. In this plot the VHYS (%) represents the separation as percentages of the nominal output voltage (VOUTx).
D. In this plot, the VOFF error in % is normalized with respect to the full-scale voltage (or VOUTx).