DLPU100A May 2020 – April 2024 DLP3021-Q1
Table 3-4 specifies the configuration and initialization timing during FPGA start-up. After Host_irq gets set high, the FPGA is configured and ready to receive commands on the SPI interface. However, the first commands will not be executed for an additional 10 ms.
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
tinit(2) | FPGA configuration initialization. 1.8V power to DONE rising edge | 230 | ms | ||
toez | DONE rising edge to DMD RESET OEZ low | 8.5 | ms | ||
tirq(3) | RESET OEZ low to HOST IRQ high | 1.15 | ms | ||
tramp(1) | Ramp time for each power supply: 1.0V, 1.8V, and 3.3V (GND to 90% reference points) | 0.2 | 50 | ms |