DLPU100A May   2020  – April 2024 DLP3021-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Purpose and Scope
  5. 2FPGA Pin Configuration and Functions
    1. 2.1 DMD Interface
    2. 2.2 Light Control
    3. 2.3 Communication
    4. 2.4 Support
    5. 2.5 FPGA Dedicated Pins
    6. 2.6 Power and Ground
    7. 2.7 Unused Pins
  6. 3Specifications
    1. 3.1 Recommended Operating Conditions
    2. 3.2 FPGA Power Consumption
    3. 3.3 Host SPI Interface Timing
    4. 3.4 Power Supply and Reset Timing
      1. 3.4.1 Power-Up Timing
      2. 3.4.2 Power-Down Timing
      3. 3.4.3 Brownout Detection
    5. 3.5 DMD Interface Timing
    6. 3.6 Flash Memory Interface Timing
    7. 3.7 Reference Clock Timing
    8. 3.8 I2C Interface Timing
  7. 4Feature Descriptions
    1. 4.1 Video Control
      1. 4.1.1 Video Options
      2. 4.1.2 Example 1: Display a Static Image
      3. 4.1.3 Example 2: Display 1 Video Repeatedly
      4. 4.1.4 Example 3: Display Two Videos Then Stop
      5. 4.1.5 Example 4: Display a Video Once and Then Display an Image Forever
      6. 4.1.6 Example 5: Display 3+ Videos/Images Seamlessly
    2. 4.2 Temperature Measurements
    3. 4.3 PWM Outputs
    4. 4.4 Host IRQ Interrupt Signal
    5. 4.5 Video and Image Compression
  8. 5Layout
  9. 6Host Command Protocol
    1. 6.1 SPI Specifications
    2. 6.2 SPI Write Command
    3. 6.3 SPI Read Command
  10. 7FPGA Register Definitions
  11. 8Revision History

2.1 DMD Interface

Table 2-1 DMD Interface Pin Descriptions
PIN I/O DESCRIPTION
NAME NUMBER POWER TYPE
D0 L14 1.8V O DMD data pins
D1 L13 1.8V O
D2 J14 1.8V O
D3 K12 1.8V O
D4 H12 1.8V O
D5 K13 1.8V O
D6 G14 1.8V O
D7 H14 1.8V O
D8 H13 1.8V O
D9 G12 1.8V O
D10(1) F14 1.8V O
D11(1) E12 1.8V O
D12(1) E13 1.8V O
D13(1) F13 1.8V O
D14(1) D14 1.8V O
DCLK B14 1.8V O DMD data clock (DDR)
TRC C14 1.8V O DMD data toggle rate control
LOADB C13 1.8V O DMD data load signal (active low)
SAC BUS M14 1.8V O DMD SAC bus data
SAC CLK N13 1.8V O DMD SAC bus clock
DAD BUS N14 1.8V O DMD DAD bus data
DMD TDO(1) P12 1.8V I DMD interface test data input. Signal connected to DMD JTAG interface to allow the verification of the interface. This signal connects to the DMD JTAG TDO. Includes an internal pullup resister.
DMD JTAG functionality is not implemented in the FPGA design. This pin can be left disconnected.
DMD TDI(1) P10 1.8V O DMD interface test data output. Signal connected to DMD JTAG interface to allow the verification of the interface. This signal connects to the DMD JTAG TDI.
DMD JTAG functionality is not implemented in the FPGA design. This pin can be left disconnected.
DMD TCK(1) P11 1.8V O DMD interface test data input. Signal connected to DMD JTAG interface to allow the verification of the interface. This signal connects to the DMD JTAG TDO.
DMD JTAG functionality is not implemented in the FPGA design. This pin can be left disconnected.
DMD TMS(1) M10 1.8V O DMD interface test mode. Signal connected to DMD JTAG interface to allow the verification of the interface.
DMD JTAG functionality is not implemented in the FPGA design. This pin can be left disconnected.
RESET OEZ P13 1.8V O DMD DAD output enable (active low). A pullup to the 1.8-V rail for the DMD interface is needed to keep this signal inactive when tri-stated.
SCTRL A13 1.8V O DMD data serial control signal
RESET STROBE M12 1.8V O DMD DAD bus strobe
(1) This pin is not applicable to the DLP2021-Q1.