DLPU130 December   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Additional Image
    2. 2.2 Power Requirements
    3. 2.3 Connector/Header Information
    4. 2.4 Boot Mode Pin Mapping
    5. 2.5 Debug Information
  8. 3Software
    1. 3.1 Software Installation
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks

2.4 Boot Mode Pin Mapping

Table 2-2 J10-Boot Mode Pin Mapping
BOOT MODE SPI0_D0_pad (SOP3) SPI0_CLK_pad (SOP2) QSPI_D1 (SOP1) QSPI_D0 (SOP0)
QSPI (4S) - Quad Read Mode 0 0 0 0
UART 0 0 0 1
QSPI (1S) - Single Read Mode 0 0 1 0
QSPI (4S) - Quad Read UART Fallback Mode 0 1 0 0
QSPI (1S) - Single Read UART Fallback Mode 0 1 0 1
DevBoot 1 0 1 1
Unsupported Bood Mode All other combinations not defined above