# Target mode, 16 bit 1-channel TDM
# BCLK in=320kHz, WCLK in=20kHz, PDMCLK out=800kHz, CLKOUT = 12.8MHz
# CLKOUT on GPIO1, PDMCLK on GPIO2

w a0 00 00 #Set page 0
w a0 01 01 #Software Reset
w a0 02 09 #Wake up with AVDD > 2v and all VDDIO level
w a0 0a b1 #GPIO1 = CLKOUT
w a0 0b 41 #GPIO2 = PDMCLK output
w a0 1a 00 #PASI TDM, 16 bit format
w a0 1e 20 #PASI DOUT Ch1 on TDM slot 0
w a0 28 20 #PASI DIN Ch1 on TDM slot 0
w a0 32 6f #FS bin=27, 5% tolerance, custom clock configuration
w a0 34 00 #PLL enabled, fraction mode disabled (D=0000), BCLK is input clock source
w a0 37 20 #PASI/SASI in target configuration (default setting)

w a0 00 03 #page 3
w a0 32 00 #(default) PLL_PDIV_IN is PASI BCLK, PASI BCLK divider source is PLL output
w a0 34 10 #(default) NM div input clock is PLL output
w a0 35 01 #(default) P=1
w a0 36 80 #J MSB=1
w a0 37 00 #D=0000
w a0 38 40 #J LSB=0100 0000 (J=320)
w a0 39 30 #NDIV=1, PDM_DIV=16
w a0 3a 22 #DIG_ADC_MODCLK_DIV=4, mdiv=8
w a0 3b 20 #DIG_DAC_MODCLK_DIV=4, DAC MOD clock 2x enabled (3.072 mode)
w a0 3e 08 #ANA_NM_DIV=8
w a0 44 07 #NDIV, MDIV, PDM_DIV enabled
w a0 45 f0 #MODCLK DIV enabled
w a0 46 05 #CLKOUT source = DSP clock (output of NDIV)
w a0 47 88 #CLKOUT divider enabled, value=8

w a0 00 00 #page 0
w a0 50 00 #(default) ADC Ch1 diff input, 5KOhm, 2Vrms AC-coupled, audio bandwidth
w a0 65 20 #(default) OUT1P LINEOUT, 0dB, DAC ch1 audio bandwidth
w a0 76 88 #enable input channel 1 and output channel 1
w a0 77 08 #different ADC MOD CLK and PDM CLK in dynamic power up/down
w a0 78 e0 #Power up all DAC+ADC channels