JAJSDF7A January 2017 – May 2017 LMK61E0M
PRODUCTION DATA.
LVCMOS channel inversion is controlled by the OUT0_INV and OUT1_INV registers.
BIT NO. | FIELD | TYPE | RESET | EEPROM | DESCRIPTION | |
---|---|---|---|---|---|---|
[7:6] | RESERVED | - | - | N | Reserved. | |
[5] | OUT1_INV | RW | 0 | Y | Inversion for CMOS output channel 1. | |
[4] | OUT0_INV | RW | 0 | Y | Inversion for CMOS output channel 0. | |
[3:0] | RESERVED | - | - | N | Reserved. |