JAJSDF7A January 2017 – May 2017 LMK61E0M
PRODUCTION DATA.
Sets R divider and CMOS OUT1 control for LMK61E0M.
BIT NO. | FIELD | TYPE | RESET | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:5] | RESERVED | - | - | N | Reserved. |
[4] | OUT1_HIZ | RW | 1 | Y | Controls OUT1 in LMK61E0M. When set to 1, the output is tri-stated with high impedance. When set to 0, the output is in normal operation. |
[3:1] | RESERVED | - | - | N | Reserved. |
[0] | PLL_RDIV | RW | 0 | Y | On LMK61E0M, R divider is set to divide-by-4 when set to 1 and R divider is bypassed when set to 0. |