JAJSSL4A December   2023  – September 2024 LMX1214

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power-On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
      4. 6.3.4 AUXCLK Output
        1. 6.3.4.1 AUXCLKOUT Output Format
        2. 6.3.4.2 AUXCLK_DIV_PRE and AUXCLK_DIV Dividers
      5. 6.3.5 SYNC Input Pins
        1. 6.3.5.1 SYNC Pins Common-Mode Voltage
        2. 6.3.5.2 Windowing Feature
    4. 6.4 Device Functional Modes Configurations
      1. 6.4.1 Pin Mode Control
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYNC Input Configuration
      2. 8.1.2 Treatment of Unused Pins
      3. 8.1.3 Current Consumption
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

7.1 Device Registers

Table 7-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7-1 must be considered as reserved locations and the register contents must not be modified.

Table 7-1 DEVICE Registers
Offset Acronym Description Section
0x0 R0 Section 7.1.1
0x2 R2 Section 7.1.2
0x3 R3 Section 7.1.3
0x4 R4 Section 7.1.4
0x5 R5 Section 7.1.5
0x7 R7 Section 7.1.6
0x8 R8 Section 7.1.7
0x9 R9 Section 7.1.8
0xB R11 Section 7.1.9
0xC R12 Section 7.1.10
0xD R13 Section 7.1.11
0xE R14 Section 7.1.12
0xF R15 Section 7.1.13
0x17 R23 Section 7.1.14
0x18 R24 Section 7.1.15
0x19 R25 Section 7.1.16
0x4B R75 Section 7.1.17
0x4F R79 Section 7.1.18
0x56 R86 Section 7.1.19
0x5A R90 Section 7.1.20

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 Device Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.1.1 R0 Register (Offset = 0x0) [Reset = 0x0000]

R0 is shown in Table 7-3.

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Table 7-3 R0 Register Field Descriptions
Bit Field Type Reset Description
15-3 UNDISCLOSED R 0x0 Program this field to 0x0.
2 POWERDOWN R/W 0x0 Sets the device in a low-power state. The states of other registers are maintained.
1-0 UNDISCLOSED R/W 0x0 Program this field to 0x0.

7.1.2 R2 Register (Offset = 0x2) [Reset = 0x0223]

R2 is shown in Table 7-4.

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Table 7-4 R2 Register Field Descriptions
Bit Field Type Reset Description
15-11 UNDISCLOSED R 0x0 Program this field to 0x0.
10-6 UNDISCLOSED R/W 0x8 Program this field to 0x8.
5 SMCLK_EN R/W 0x1 Enables the state machine clock generator. This is required for pin modes to function correctly and the part must be initialized with this bit enabled. However, this bit can later on be disabled to save current and prevent the state machine clock spur.
4-0 UNDISCLOSED R/W 0x3 Program this field to 0x3.

7.1.3 R3 Register (Offset = 0x3) [Reset = 0xF0FE]

R3 is shown in Table 7-5.

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Table 7-5 R3 Register Field Descriptions
Bit Field Type Reset Description
15 CLKOUT3_EN R/W 0x1 Enables CLKOUT3
14 CLKOUT2_EN R/W 0x1 Enables CLKOUT2
13 CLKOUT1_EN R/W 0x1 Enables CLKOUT1
12 CLKOUT0_EN R/W 0x1 Enables CLKOUT0
11-0 UNDISCLOSED R/W 0xFE Program this field to 0xFE.

7.1.4 R4 Register (Offset = 0x4) [Reset = 0x36FF]

R4 is shown in Table 7-6.

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Table 7-6 R4 Register Field Descriptions
Bit Field Type Reset Description
15-14 UNDISCLOSED R 0x0 Program this field to 0x0.
13-11 CLKOUT1_PWR R/W 0x6 Sets the output power of CLKOUT1. Larger values correspond to higher output power.
10-8 CLKOUT0_PWR R/W 0x6 Sets the output power of CLKOUT0. Larger values correspond to higher output power.
7-0 UNDISCLOSED R/W 0xFF Program this field to 0xFF.

7.1.5 R5 Register (Offset = 0x5) [Reset = 0x36F6]

R5 is shown in Table 7-7.

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Table 7-7 R5 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0x0 Program this field to 0x0.
14-6 UNDISCLOSED R/W 0xDB Program this field to 0xDB.
5-3 CLKOUT3_PWR R/W 0x6 Sets the output power of CLKOUT3. Larger values correspond to higher output power.
2-0 CLKOUT2_PWR R/W 0x6 Sets the output power of CLKOUT2. Larger values correspond to higher output power.

7.1.6 R7 Register (Offset = 0x7) [Reset = 0x543F]

R7 is shown in Table 7-8.

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Table 7-8 R7 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0x0 Program this field to 0x0.
14-13 UNDISCLOSED R/W 0x2 Program this field to 0x2.
12-11 AUXCLKOUT_VCM R/W 0x2 In LVDS mode, sets the output common mode of the auxiliary clock output. Other output formats ignore this field.
0x0 = 1.2V
0x1 = 1.1V
0x2 = 1.0V
0x3 = 0.9V
10-9 UNDISCLOSED R/W 0x2 Program this field to 0x2.
8-7 AUXCLK_DIV_PWR_PRE R/W 0x0 Sets the output power of the AUXCLK pre-driver. Larger values correspond to higher output power.
6-4 UNDISCLOSED R/W 0x3 Program this field to 0x3.
3-1 AUXCLKOUT_PWR R/W 0x7 Sets the output power of AYXCLKOUT for CML format only (other output formats ignore this field). Larger values correspond to higher output power.
0 UNDISCLOSED R/W 0x1 Program this field to 0x1.

7.1.7 R8 Register (Offset = 0x8) [Reset = 0x0120]

R8 is shown in Table 7-9.

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Table 7-9 R8 Register Field Descriptions
Bit Field Type Reset Description
15-9 UNDISCLOSED R 0x0 Program this field to 0x0.
8-6 AUXCLK_DIV_PRE R/W 0x4 Sets pre-divider value. Output of the pre-divider must be less than or equal to 3.2 GHz. When AUXCLK_DIV_PRE=1, register R79 is also required to be programmed to a value of 0x0005 and R90 to 0x0060 (AUXCLK_DIV_BYP2=1, AUXCLK_DIV_BYP3=1). Values for AUXCLK_DIV_PRE other than those listed below are reserved.
0x1 = /1
0x2 = /2
0x4 = /4
5 AUXCLKOUT_EN R/W 0x1 Enables AUXCLK subsystem.
4-2 UNDISCLOSED R/W 0x0 Program this field to 0x0.
1-0 AUXCLKOUT_FMT R/W 0x0 Selects the output driver format of the AUXCLKOUT output.
0x0 = LVDS
0x1 = Reserved
0x2 = CML
0x3 = Reserved

7.1.8 R9 Register (Offset = 0x9) [Reset = 0x0020]

R9 is shown in Table 7-10.

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Table 7-10 R9 Register Field Descriptions
Bit Field Type Reset Description
15-14 SYNC_VCM R/W 0x0 Sets the internal DC Bias for the SYNC pins. Bias must be enabled for AC-coupled inputs; but can be enabled and overdriven, or disabled, for DC-coupled inputs. SYNC DC pin voltage must be in the range of 0.7 V to VCC, including minimum and maximum signal swing.
0x0 = 1.3V
0x1 = 1.1V
0x2 = 1.5V
0x3 = Disabled
13 SYNC_EN R/W 0x0 Enables synchronization path for the dividers and allows the clock position capture circuitry to be enabled. Used for multi-device synchronization.
12 UNDISCLOSED R/W 0x0 Program this field to 0x0.
11 AUXCLK_DIV_BYP R/W 0x0 Bypasses the AUXCLK_DIV divider to derive the AUXCLK output directly from the AUXCLK_DIV_PRE divider. Use only when AUXCLK_DIV_PRE=1 as one of the steps to achieve a total divide of 1 for the AUXCLK. To achieve a divide by 1, the following steps are required.
1. Set AUXCLK_DIV_PRE=1
2. Verify that register R79 is programmed to a value of 0x0005
3. Program R90 to 0x0060 (AUXCLK_DIV_BYP2=1, AUXCLK_DIV_BYP3=1)
4. Set AUXCLK_DIV_BYP=1

If a total divide of 1 for the AUXCLK is undesired, set this bit to 0.
10 UNDISCLOSED R/W 0x0 Program this field to 0x0.
9-0 AUXCLK_DIV R/W 0x20 Sets AUXCLK divider value. Maximum input frequency from AUXCLK_DIV_PRE must be ≤ 3200 MHz. The maximum AUXCLKOUT frequency must be ≤ 800 MHz to avoid amplitude degradation.
0x0 = Reserved
0x1 = Reserved
0x2 = /2
0x3 = /3
0x3FF = /1023

7.1.9 R11 Register (Offset = 0xB) [Reset = 0x0000]

R11 is shown in Table 7-11.

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Table 7-11 R11 Register Field Descriptions
Bit Field Type Reset Description
15-0 rb_CLKPOS R 0x0 Stores a snapshot of the CLKIN signal rising edge positions relative to a SYNC rising edge, with the snapshot starting from the LSB and ending at the MSB. Each bit represents a sample of the CLKIN signal, separated by a delay determined by the SYNC_DLY_STEP field. The first and last bits of rb_CLKPOS are always set, indicating uncertainty at the capture window boundary conditions. CLKIN rising edges are represented by every sequence of two set bits from LSB to MSB, including bits at the boundary conditions. The position of the CLKIN rising edges in the snapshot, along with the CLKIN signal period and the delay step size, can be used to compute the value of SYNC_DLY which maximizes setup and hold times for SYNC signals on the SYNC pins.

7.1.10 R12 Register (Offset = 0xC) [Reset = 0x0000]

R12 is shown in Table 7-12.

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Table 7-12 R12 Register Field Descriptions
Bit Field Type Reset Description
15-0 rb_CLKPOS[31:16] R 0x0 MSB of rb_CLKPOS field.

7.1.11 R13 Register (Offset = 0xD) [Reset = 0x0003]

R13 is shown in Table 7-13.

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Table 7-13 R13 Register Field Descriptions
Bit Field Type Reset Description
15-2 UNDISCLOSED R 0x0 Program this field to 0x0.
1-0 SYNC_DLY_STEP R/W 0x3 Sets the step size of the delay element used in the SYSNC path, both for SYNC input delay and for clock position captures. The recommended frequency range for each step size creates the maximum number of usable steps for a given CLKIN frequency. The ranges include some overlap to account for process and temperature variations. If the CLKIN frequency is covered by an overlapping span, larger delay step sizes improve the likelihood of detecting a CLKIN rising edge during a clock position capture. However, since larger values include more delay steps, larger step sizes have greater total delay variation across PVT relative to smaller step sizes.
0x0 = 28 ps (1.4GHz to 2.7GHz)
0x1 = 15 ps ( 2.4GHz to 4.7GHz)
0x2 = 11 ps (3.1GHz to 5.7GHz)
0x3 = 8 ps (4.5GHz to 12.8GHz)

7.1.12 R14 Register (Offset = 0xE) [Reset = 0x0002]

R14 is shown in Table 7-14.

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Table 7-14 R14 Register Field Descriptions
Bit Field Type Reset Description
15-3 UNDISCLOSED R/W 0x0 Program this field to 0x0.
2 CLKPOS_CAPTURE_EN R/W 0x0 Enables the windowing circuit which captures the clock position in the rb_CLKPOS registers with respect to a SYNC edge. The windowing circuit must be cleared by toggling SYNC_CLR high then low before a clock position capture. The first rising edge on the SYNC pins after clearing the windowing circuit triggers the capture. The capture circuitry greatly increases supply current, and does not need to be enabled to delay the SYNC signal in SYNC mode. Once the desired value of SYNC_DLY is determined, set this bit to 0x0 to minimize current consumption. If SYNC_EN = 0, the value of this bit is ignored, and the windowing circuit is disabled.
1 UNDISCLOSED R/W 0x1 Program this field to 0x1.
0 SYNC_LATCH R/W 0x0 Latches the internal SYNC state to logic high on the first rising edge of the SYNC pins. This latch can be cleared by setting SYNC_CLR=1.

7.1.13 R15 Register (Offset = 0xF) [Reset = 0x0B01]

R15 is shown in Table 7-15.

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Table 7-15 R15 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R 0x0 Program this field to 0x0.
11-7 UNDISCLOSED R/W 0x16 Program this field to 0x16.
6-1 SYNC_DLY R/W 0x0 Sets the delay line step for the external SYNC signal. Each delay line step delays the SYNC signal by an amount equal to SYNC_DLY_STEP x SYNC_DLY_STEP. In SYNC mode, the value for this field can be determined based on the rb_CLKPOS value to satisfy the internal setup and hold time of the SYNC signal with respect to the CLKIN signal. In SYSREF Repeater Mode, the value for this field can be used as a coarse global delay. Values greater than 0x3F are invalid. Since larger values include more delay steps, larger values have greater total step size variation across PVT relative to smaller values. Refer to the data sheet or the device TICS Pro profile for detailed description of the delay step computation procedure.
0 SYNC_CLR R/W 0x1 Clears SYNC_LATCH and resets synchronization path timing for SYNC signal. Holding this bit high keeps internal SYNC signal low. This bit must be set and cleared once before the SYNC or clock position capture operations are performed.

7.1.14 R23 Register (Offset = 0x17) [Reset = 0x4000]

R23 is shown in Table 7-16.

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Table 7-16 R23 Register Field Descriptions
Bit Field Type Reset Description
15 TS_EN R/W 0x0 Enables the on-die temperature sensor. Temperature sensor counter (TS_CNT_EN) must also be enabled for readback.
14 UNDISCLOSED R/W 0x1 Program this field to 0x1.
13 MUXOUT_EN R/W 0x0 Enables or tri-states the MUXOUT pin driver.
0x0 = Tri-States
0x1 = Push-Pull
12-0 UNDISCLOSED R/W 0x0 Program this field to 0x0.

7.1.15 R24 Register (Offset = 0x18) [Reset = 0x0000]

R24 is shown in Table 7-17.

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Table 7-17 R24 Register Field Descriptions
Bit Field Type Reset Description
15-14 UNDISCLOSED R 0x0 Program this field to 0x0.
13-12 UNDISCLOSED R/W 0x0 Program this field to 0x0.
11-1 rb_TS R 0x0 Readback value of on-die temperature sensor.
0 TS_CNT_EN R/W 0x0 Enables temperature sensor counter. Temperature sensor (TS_EN) must be enabled for accurate data.

7.1.16 R25 Register (Offset = 0x19) [Reset = 0x0211]

R25 is shown in Table 7-18.

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Table 7-18 R25 Register Field Descriptions
Bit Field Type Reset Description
15-7 UNDISCLOSED R/W 0x4 Program this field to 0x4.
6 CLK_DIV_RST R/W 0x0 Resets the main clock divider. If the clock divider value is changed during operation, set this bit high then low after setting the new divider value. Synchronizing the device with the SYNC pins with SYNC_EN = 0x1 also resets the main clock divider. This bit has no effect when outside of Divider Mode.
5-3 CLK_DIV R/W 0x2 Sets the clock divider value when CLK_MUX=2 (Divider Mode). The clock divider value is CLK_DIV+1. Valid value for CLK_DIV is 1 to 7. Setting this to 0 disables the main clock divider and reverts to buffer mode.
2-0 CLK_MUX R/W 0x1 Selects the function for the main clock outputs
0x0 = Reserved
0x1 = Buffer
0x2 = Divider
0x3 = Reserved

7.1.17 R75 Register (Offset = 0x4B) [Reset = 0x0006]

R75 is shown in Table 7-19.

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Table 7-19 R75 Register Field Descriptions
Bit Field Type Reset Description
15 rb_CLKOUT2_EN R 0x0 Readback Pin Status
14 rb_CLKOUT1_EN R 0x0 Readback Pin Status
13 rb_CLKOUT0_EN R 0x0 Readback Pin Status
12 rb_MUXSEL1 R 0x0 Readback Pin Status
11-7 UNDISCLOSED R 0x0 Program this field to 0x0.
6 rb_DIVSEL1 R 0x0 Readback Pin Status
5 rb_DIVSEL0 R 0x0 Readback Pin Status
4 rb_CE R 0x0 Readback Pin Status
3-0 UNDISCLOSED R/W 0x6 Program this field to 0x6.

7.1.18 R79 Register (Offset = 0x4F) [Reset = 0x0205]

R79 is shown in Table 7-20.

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Table 7-20 R79 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0x0 Program this field to 0x0.
14-0 UNDISCLOSED R/W 0x205 Program this field to 0x5. Note that this is different than the reset value.

7.1.19 R86 Register (Offset = 0x56) [Reset = 0x0000]

R86 is shown in Table 7-21.

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Table 7-21 R86 Register Field Descriptions
Bit Field Type Reset Description
15-3 UNDISCLOSED R/W 0x0 Program this field to 0x0.
2 MUXOUT_EN_OVRD R/W 0x0 This bit must be set to 1 to enable MUXOUT_EN to tri-state the MUXOUT pin.
1-0 UNDISCLOSED R/W 0x0 Program this field to 0x0.

7.1.20 R90 Register (Offset = 0x5A) [Reset = 0x0000]

R90 is shown in Table 7-22.

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Table 7-22 R90 Register Field Descriptions
Bit Field Type Reset Description
15-8 UNDISCLOSED R 0x0 Program this field to 0x0.
7 UNDISCLOSED R/W 0x0 Program this field to 0x0.
6 AUXCLK_DIV_BYP3 R/W 0x0 Set this bit to 1 if AUXCLK_BYP=1, set to 0 otherwise.
5 AUXCLK_DIV_BYP2 R/W 0x0 Set this bit to 1 if AUXCLK_BYP=1, set to 0 otherwise.
4-0 UNDISCLOSED R/W 0x0 Program this field to 0x0.