SBAA222A October 2017 – April 2025 ADS1282-SP
This document presents an overview of the single event effect (SEE) testing and a summary of the observed results. Testing for single-event latch-up (SEL), single-event functional interrupt (SEFI) and single-event transient (SET) events was performed at the Cyclotron Institute at Texas A&M University using the K500 Cyclotron and the 15 MeV/n beam. The ASTM F1192 [4] and EIA/JESD57 [5] standards were used as reference for this testing. The test plan was outlined by Texas Instruments and the task was contracted to Aeroflex RAD [6].
The SEL testing was performed to determine the threshold for latch-up under worst-case temperature and voltage operating conditions, up to a LET of 81MeV × cm2/ mg. Maximum fluence of 107 ions / cm2 was used to irradiate at temperatures of 85°C and 125°C. The SEU rates were characterized for a given LET range between 2.7MeV × cm2/ mg and 52.3 MeV × cm2/ mg at a maximum fluence of 106 ions / cm2 or until 100 SETs were recorded. Since the ADS1282-SP has configuration registers, the register SEU rates were characterized in addition to the data conversion SEU rates.
| DESCRIPTION | DEVICE INFORMATION |
|---|---|
| TI Part Number | ADS1282-SP |
| SMD Number | 5962-14231 |
| Device Function | Analog-to-digital conversion |
| Technology | 50HPA07 |
| Exposure Facility | Radiation Effects Facility, Cyclotron, Texas A&M University |
| Heavy Ion Fluence per run | 106 ions/cm2 to 107 ions/cm2 |
| Irradiation Temperature | 85°C, and 125°C (for SEL testing) |
Since the ADS1282-SP device does not operate at high voltages or high currents, single-event burn-out (SEB) and single-event gate-rupture (SEGR) events are not expected to be an issue. The primary single-event effect (SEE) events of interest in the ADS1282-SP are SEL, SEFI, and SET.
From a risk and impact point-of-view, the occurrence of an SEL is potentially the most disruptive SEE event and the biggest concern for space applications. In mixed technologies such as BiCMOS HPA07 250nm process used for the ADS1282-SP, the CMOS circuitry introduces a potential SEL susceptibility. SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-substrate and n-well and n+ and p+ contacts) [7], [8]. The parasitic bipolar structure creates a high-conductance path (creating a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is latched) until power is removed or until the device is destroyed by the high-current state. For the design of the ADS1282-SP, SEL-susceptibility was reduced by maximizing the number of well and substrate ties in the CMOS portions of the layout. The design techniques applied for latch-up mitigation were sufficient as the ADS1282-SP exhibited no signs of SEL with heavy-ions of LETeff = 50.5 MeV×cm2/ mg at a fluence of 107 ions / cm2 and a chip temperature of 125°C nor were any latch-up events detected up to an LETeff = 60.4MeV×cm2/ mg at 85°C.
In devices such as the ADS1282-SP delta-sigma ADC single events large enough to effect a circuit is expected to manifest either as an upset in the control logic or the signal chain itself causing either a system reset or misoperation, or, more likely, an error in the ADC output. SEFIs might occur if sequential circuits in the control logic, calibration or serial interface are upset by a single-event. Single-events occurring in the signal chain, preamplifier, modulator, LDO are likely to cause a short-lived error on output samples (a single sample or a small set of contiguous samples) with no other operational changes in the device performance.