SLAA890A December 2019 – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2422 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133
Sampling (sample-and-hold) time determines how long to sample a signal before digital conversion. During sample time, an internal switch allows the input capacitor to be charged. The required time to fully charge the capacitor is dependent on the external analog front-end (AFE) connected to the ADC input pin. Figure 3-3 shows a typical ADC model of an MSP430 MCU. The RI and CI values can be obtained from the device-specific data sheet.
It is critical to understand the AFE drive capability. If possible, model the AFE as shown in Figure 3-2. After this is known, calculate the minimum sampling time required to sample the signal. The resistance of the sources (RS and RI) affects tsample. Equation 4 can be used to calculate a conservative value of the minimum sample time tsample for an n-bit conversion.
More simple models can be adopted based on a common RS assumption. According to the MSP430FR235x, MSP430FR215x data sheet, the sampling time of the ADC (tSample), which is the minimal value, should be calculated on (CI + Cexternal) × (RS + RI) × Tau. The meaning of the "minimal value of sampling time" is the minimum time that is required to result in an error of less than ±0.5 LSB at the defined condition.
PARAMETER | TEST CONDITIONS | DEVICE GRADE | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fADCCLK | ADC clock frequency | ADC clock, 10-bit mode | T | 2.4 V to 3.6 V | 6.0 | MHz | |
ADC clock, 12-bit mode | 4.4 | ||||||
tSettling | Turn-on settling time of the ADC(1) | The error in a conversion started after tADCON is less than ±0.5 LSB, Reference and input signal already settled | T | 100 | ns | ||
tSample | Sampling time | RS = 1000 Ω, RI = 4000 Ω, CI = 5.5 pF, Cexternal = 8.0 pF, Approximately 7.62 Tau (t) are required for an error of less than ±0.5 LSB, 10-bit mode | T | 2.4 V to 3.6 V | 0.52 | µs | |
RS = 1000 Ω, RI = 4000 Ω, CI = 5.5 pF, Cexternal = 8.0 pF, Approximately 9.01 Tau (t) are required for an error of less than ±0.5 LSB, 12-bit mode | T | 2.4 V to 3.6 V | 0.61 |
The sample-and-hold time depends on the mode (pulse sample mode or extended sample mode). The ADCSHTx bit controls the sample-and-hold time only in pulse sample mode. A timer can be used to control the sample-and-hold time in extended sample mode, providing more granular control.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | ADCSHTx | ||||||
r0 | r0 | r0 | r0 | rw-(0) | rw-(0) | rw-(0) | rw-(1) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCMSC | Reserved | ADCON | Reserved | ADCENC | ADCSC | ||
rw-(0) | r0 | r0 | rw-(0) | r0 | r0 | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
11-8 | ADCSHTx | RW | 1h(1) | ADC sample-and-hold time. These bits define the number of ADCCLK cycles in the sampling period for the ADC. Can be modified only when ADCENC = 0. Resetting ADCENC = 0 by software and changing these fields immediately shows an effect when a conversion is active. 0000b = 4 ADCCLK cycles 0001b = 8 ADCCLK cycles 0010b = 16 ADCCLK cycles 0011b = 32 ADCCLK cycles 0100b = 64 ADCCLK cycles 0101b = 96 ADCCLK cycles 0110b = 128 ADCCLK cycles 0111b = 192 ADCCLK cycles 1000b = 256 ADCCLK cycles 1001b = 384 ADCCLK cycles 1010b = 512 ADCCLK cycles 1011b = 768 ADCCLK cycles 1100b = 1024 ADCCLK cycles 1101b = 1024 ADCCLK cycles 1110b = 1024 ADCCLK cycles 1111b = 1024 ADCCLK cycles |
With the conditions of VCC = 2.4 V to 3.6 V and resolution = 12 bits, the minimum ADC sampling time is Equation 5.
In this formula, RS = 1000 Ω and Cexternal = 8.0 pF are the assumed values for the common case. 9.01 Tau, RI = 4000 Ω, and CI = 5.5 pF are known values from tests and calculations.
After the minimum sample-and-hold time is calculated, the appropriate settings for the ADC can be determined including selecting the correct ADC clock. The key goal is to optimize the sample-and-hold time in the application. If the sample-and-hold time is excessively longer than required, it is a waste of energy for the ADC to be operational during that time. The sample-and-hold time also limits the maximum sample rate. If your application requires a larger sample-and-hold time than the minimum, there is a tradeoff between performance and maximum sample rate.