SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The purpose of the CRC engine is to accelerate CRC and TCP checksum operation. The result of the CRC operation is a 32- and 16-bit signature which can be used to check the sanity of data. The required mode of operation is selected through the TYPE bit in the CRC Control (CRCCTRL) register, offset 0x400. A µDMA software channel can be used to burst data into the CRC module. CRCs are computed combinatorially in one clock.
The CRC module contains all of the control registers to which the input context interfaces. Because CRC calculations are a single cycle, as soon as data is written to CRC Data Input (CRCDIN) register, the result of CRC/CSUM is updated in the CRC SEED/Context (CRCSEED) register, offset 0x410. The input data is computed by the selected CRC polynomial or CSUM.