SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 7-42 lists the memory-mapped registers for the system control memory. All register offset addresses not listed in Table 7-42 should be considered as reserved locations and the register contents should not be modified.
Offsets are relative to the System Control base address of 0x400FE000.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0xD4 | RVP | Reset Vector Pointer | Section 7.5.1 |
| 0x1D0 | BOOTCFG | Boot Configuration | Section 7.5.2 |
| 0x1E0 to 0x1EC | USER_REG_0 to USER_REG_3 | User Register 0 to User Register 3 | Section 7.5.3 |
| 0x200 to 0x23C | FMPRE_0 to FMPRE_15 | Flash Memory Protection Read Enable 0 to Flash Memory Protection Read Enable 15 | Section 7.5.4 |
| 0x400 to 0x43C | FMPPE_0 to FMPPE_15 | Flash Memory Protection Program Enable 0 to Flash Memory Protection Program Enable 15 | Section 7.5.5 |
Complex bit access types are encoded to fit into small table cells. Table 7-43 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |